Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Patent metadata

Field	Value
Publication number	US-9620494-B2
Application number	US-201615260723-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Dec 15, 2010
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer.

First claim

What is claimed is:

1. A semiconductor package including a plurality of external terminals, the semiconductor package comprising:
a semiconductor chip including a plurality of chip pads, the chip pads having a first pitch;
a first layer on the semiconductor chip, the first layer formed of a first organic material, the first layer including,
a plurality of first conductive patterns on a bottom surface of the first layer, the first conductive patterns having a second pitch, the first conductive patterns connected to the chip pads,
a plurality of second conductive patterns on a top surface of the first layer, the second conductive patterns having a third pitch, the third pitch being greater than the first pitch, and
a plurality of circuit patterns connecting the first conductive patterns with the second conductive patterns;

a second layer on the first layer, the second layer formed of a second organic material different from the first organic material, the second layer including,
a plurality of first vias penetrating the second layer, and
a plurality of third conductive patterns on a top surface of the second layer, the first was connecting the second conductive patterns with the third conductive patterns; and

a third layer on the second layer, the third layer formed of the second organic material, the third layer including,
a plurality of second vias penetrating the third layer, the second vias connecting the third conductive patterns with the external terminals.

2. The semiconductor package of claim 1 , wherein the first pitch is equal to or less than 10 μm and the third pitch is equal to or greater than 20 μm.

3. The semiconductor package of claim 1 , wherein the first organic material is polyimide.

4. The semiconductor package of claim 1 , wherein a thickness of the first layer is equal to or less than 20 μm.

5. The semiconductor package of claim 1 , wherein
the second layer includes a core and insulation layers, the insulating layers covering the core on top and bottom surfaces of the core,
the core is formed of one of reinforced fiberglass or epoxy resin, and
the insulation layers is formed of prepreg.

6. The semiconductor package of claim 1 , wherein
the circuit pattern includes a plurality of internal patterns, a plurality of first internal vias, and a plurality of second internal vias, the first internal vias having a fourth pitch, the internal patterns having a fifth pitch greater than the fourth pitch,
the internal patterns are connected to the first conductive patterns via the first internal vias, and further are connected to the second conductive patterns via the second internal vias.

7. The semiconductor package of claim 1 , wherein the plurality of chip pads includes at least five chip pads.

8. The semiconductor package of claim 1 , further comprising:
a plurality of first solder balls connecting the chip pads to first conductive patterns, and
a plurality of second solder balls functioning as the external terminals.

9. The semiconductor package of claim 8 , wherein a pitch between the first solder balls is smaller than a pitch between the second solder balls.

10. A semiconductor package including a plurality of external terminals, the semiconductor package comprising:
a semiconductor chip including a plurality of chip pads, the chip pads having a first pitch;
a first layer on the semiconductor chip, the first layer including,
a plurality of first conductive patterns on a bottom surface of the first layer, the first conductive patterns having a second pitch, the first conductive patterns connected to the chip pads,
a plurality of second conductive patterns on a top surface of the first layer, the second conductive patterns having a third pitch greater than the first pitch, and
a plurality of circuit patterns connecting the first conductive patterns with the second conductive patterns;

a second layer on the first layer, the second layer including,
a plurality of first vias penetrating the second layer, and
a plurality of third conductive patterns on a top surface of the second layer, the third conductive patterns connected to the second conductive pattern via the first vias; and

a third layer on the second layer, the third layer including,
a plurality of second vias penetrating the third layer, the second vias connecting the third conductive patterns with the external terminals.

11. The semiconductor package of claim 10 , wherein the first pitch is equal to or less than 10 μm and the third pitch is equal to or greater than 20 μm.

12. The semiconductor package of claim 10 , wherein a thickness of the first layer is less than 10 μm.

13. The semiconductor package of claim 10 , wherein the first layer is an inorganic layer, and the second and third layers are organic layers.

14. The semiconductor package of claim 13 , wherein the inorganic layer includes one of a silicon-oxide (SiO 2 ), a silicon nitride (SiN), or any combination thereof.

15. The semiconductor package of claim 10 , wherein
the circuit pattern includes a plurality of internal patterns, a plurality of first internal vias, and a plurality of second internal vias, the internal patterns having a fourth pitch, a pitch between the first internal vias being smaller than a pitch between the second internal vias,
the internal patterns are connected to the first conductive patterns via the first internal vias, and further are connected to the second conductive patterns via the second internal vias.

16. The semiconductor package of claim 10 , wherein the chip pads include at least five chip pads.

17. The semiconductor package of claim 10 , further comprising:
a plurality of first solder balls connecting the chip pads to the first conductive patterns, and
a plurality of second solder balls functioning as the external terminals.

18. The semiconductor package of claim 17 , wherein a pitch between the first solder balls is smaller than a pitch between the second solder balls.

19. A semiconductor package including a plurality of external terminals, the semiconductor package comprising:
a semiconductor chip including a plurality of chip pads and at least one through electrode, the chip pads having a first pitch;
a first layer on the semiconductor chip, the first layer formed of a first organic material the first layer including,
a plurality of first conductive patterns on a bottom surface of the first layer, the first conductive patterns having a second pitch, the first conductive patterns connected to the chip pads,
a plurality of second conductive patterns on a top surface of the first layer, the second conductive patterns having a third pitch greater than the first pitch, and
a plurality of circuit patterns connecting the first conductive patterns with the second conductive patterns;

a second layer on the first layer, the second layer formed of a second organic material different from the first organic material, the second layer including,
a plurality of first vias penetrating the second layer, and
a plurality of third conductive patterns on a top surface of the second layer, the third conductive patterns connected to the second conductive patterns via the first vias; and

a third layer on the second layer, the third layer formed of the second organic material, the third layer including,
a plurality of second was penetrating the third layer, the second vias connecting the third conductive patterns with the external terminals.

20. The semiconductor package of claim 19 , wherein the at least o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Daewoo
• Kim Chulwoo

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title