High density substrate interconnect formed through inkjet printing

Patent metadata

Field	Value
Publication number	US-9741664-B2
Application number	US-201615147411-A
Country	US
Kind code	B2
Filing date	May 5, 2016
Priority date	Sep 25, 2013
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

First claim

What is claimed is:

1. An integrated circuit package comprising:
a multidie substrate including low density routing therein, low density interconnect pads on a surface of the substrate, and a cavity formed therein;
an interconnect bridge inkjet printed and sintered in the cavity of the multidie substrate, wherein the interconnect bridge includes high density routing therein, the high density routing including traces and vias, and the high density routing including pads on a surface of the interconnect bridge, the high density routing exhibits a sintered grain morphology of inkjet printed and sintered metals, the traces including a spacing of a micrometer or less therebetween, wherein the interconnect bridge further includes dielectric material inkjet printed around the traces and the vias; and
a first die and a second die electrically coupled through the traces, vias, and pads of the interconnect bridge, wherein each of the first die and the second die at least partially overlap with the cavity.

2. The integrated circuit package of claim 1 , the first die is a memory and the second die is a processor.

3. The integrated circuit package of claim 2 , wherein the substrate is a bumpless buildup layer (BBUL) substrate.

4. The integrated circuit package of claim 3 , wherein the at least one of the one or more pads is a flip-chip pad.

5. The IC package of claim 3 , wherein the BBUL substrate includes:
a first buildup layer with first low density interconnect routing therein, the first low density interconnect routing including one or more traces, vias, and pads;
a second buildup layer on the first buildup layer and with second low density interconnect routing therein, the second low density interconnect routing electrically connected to the first low density interconnect routing.

6. The integrated circuit package of claim 5 , wherein the second buildup layer includes the cavity formed therein.

7. The integrated circuit package of claim 6 , wherein the first die and the second die are further electrically connected to the second low density interconnect routing.

8. The integrated circuit package of claim 7 , wherein the low density interconnect routing includes a routing density that is up to about 100 times less dense than the high density interconnect routing.

9. The integrated circuit package of claim 8 , wherein the BBUL substrate includes a third buildup layer, wherein the first and second dies are situated, at least partially, in the third buildup layer, the third buildup layer on the second buildup layer.

10. The integrated circuit package of claim 9 , wherein the dielectric is on and between the traces of the interconnect bridge and between the vias of the interconnect bridge, the dielectric between the second and third buildup layers, and the dielectric at least partially in the cavity.

11. The integrated circuit package of claim 8 , further comprising a molding material on the second buildup layer and between the first and second dies and the second buildup layer, the molding material at least partially surrounding the first and second dies.

12. The integrated circuit package of claim 11 , wherein the dielectric is on and between the traces of the interconnect bridge and between the vias of the interconnect bridge, the dielectric between the second buildup layer and the molding material, and the dielectric at least partially in the cavity.

13. An integrated circuit package comprising:
a multidie bumpless buildup layer (BBUL) substrate including low density interconnect circuitry at least partially therein and thereon, the low density interconnect circuitry including first traces, first vias, and first pads, the multidie substrate including a cavity formed therein;
an interconnect bridge inkjet printed in the cavity of the multidie substrate, wherein the interconnect bridge includes high density interconnect circuitry inkjet printed therein and thereon, the high density interconnect circuitry including second traces, second vias, and second pads that exhibit a sintered grain morphology of a printed and sintered metal, wherein the low density interconnect circuitry is around and under the multidie substrate, the second traces including a spacing of a micrometer or less therebetween, wherein the interconnect bridge further includes dielectric material inkjet printed around the traces and the vias; and
a first die including a third pad electrically connected to a pad of the second pads; and
a second die including a fourth pad electrically connected to another pad of the second pads so as to electrically couple the first die to the second die through the interconnect bridge, wherein each of the first die and the second die overlap with the cavity.

14. The IC package of claim 13 , wherein the low density interconnect circuitry includes first low density interconnect routing and second low density interconnect routing, wherein the BBUL substrate includes:
a first buildup layer with first low density interconnect routing therein, the first low density interconnect routing including one or more traces, vias, and pads;
a second buildup layer with second low density interconnect routing therein, the second low density interconnect routing including one or more traces and vias, the second low density interconnect routing electrically connected to the first low density interconnect routing.

15. The integrated circuit package of claim 14 , wherein the second buildup layer includes the cavity formed therein.

16. The integrated circuit package of claim 15 , wherein the first die and the second die are electrically connected through the second low density interconnect routing.

17. The integrated circuit package of claim 16 , wherein the low density interconnect circuitry includes a routing density that is up to about 100 times less dense than the high density interconnect circuitry.

18. The integrated circuit package of claim 17 , wherein the first and second dies are situated, at least partially, in a third buildup layer of the BBUL substrate, the third buildup layer on the second buildup layer.

19. The integrated circuit package of claim 18 , wherein the dielectric is on and between the traces of the interconnect bridge, the dielectric between the second and third buildup layers; and the dielectric at least partially in the cavity.

20. The integrated circuit package of claim 17 , further comprising:
a molding material on the second buildup layer and between the first and second dies and the second buildup layer, the molding material at least partially surrounding the first and second dies; and
wherein the dielectric is on and between the traces of the interconnect bridge, the dielectric between the second buildup layer and the molding material, and the dielectric at least partially in the cavity.

Assignees

• Intel Corp

Inventors

• Chiu Chia-Pin
• Ichikawa Kinya
• Sankman Robert L

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title