Inorganic interposer for multi-chip packaging

Patent metadata

Field	Value
Publication number	US-10692847-B2
Application number	US-201515755533-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.

First claim

What is claimed is:

1. A multi-chip device comprising:
a substrate including low density interconnect circuitry therein;
an inorganic interposer on and in contact with the substrate, the inorganic interposer including high density interconnect circuitry, the high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including the high density interconnect circuitry in first and second stacks of inorganic materials, and each of the first and second stacks of inorganic materials including a silicon nitride and a silicon oxide on and in contact with the silicon nitride, the silicon nitride of the first stack on and in contact with a surface of the substrate and the silicon nitride of the second stack on and in contact with a surface of the silicon oxide of the first stack; and
two or more chips electrically connected to the inorganic interposer, the two or more chips directly electrically connected to each other through the high density interconnect circuitry.

2. The device of claim 1 , wherein the inorganic interposer further includes another silicon nitride on and in contact with the silicon oxide.

3. The device of claim 1 , wherein the high density interconnect circuitry includes line widths and line spaces less than about two microns.

4. The device of claim 1 , wherein the inorganic interposer includes a dual damascene substrate.

5. The device of claim 1 , wherein the inorganic interposer includes a conductive seed material between a circuit layer and a buildup layer.

6. The device of claim 1 , wherein the two or more chips includes a logic chip and a memory chip.

7. A device comprising:
a substrate including low density interconnect circuitry therein;
an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry, the high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including the high density interconnect circuitry in first and second stacks of alternating layers of inorganic materials, each of the first and second stacks of inorganic materials including a silicon nitride on and in contact with a silicon oxide, the silicon nitride of the first stack on and in contact with a surface of the substrate and the silicon nitride of the second stack on and in contact with a surface of the silicon oxide of the first stack;
two or more chips electrically connected to the inorganic interposer, the two or more chips directly electrically connected to each other through the high density interconnect circuitry; and
a surface finish layer situated between the silicon oxide of the second stack and the two or more chips.

8. The device of claim 7 , wherein the high density interconnect circuitry includes line widths and line spaces less than about two microns.

9. The device of claim 7 , wherein the two or more chips includes a logic chip and a memory chip.

Assignees

• Intel Corp

Inventors

• Sobieski Daniel
• Darmawikarta Kristof
• Boyapati Sri Ranga Sai
• Celikkol Merve
• Lee Kyu Oh
• Aygun Kemal
• Qian Zhiguo

Classifications

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H10W70/686

  the multiple insulating layers having different compositions, e.g. polymer layer on glass substrate · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title