Double side via last method for double embedded patterned substrate

Patent metadata

Field	Value
Publication number	US-10128198-B2
Application number	US-201715495282-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Apr 24, 2015
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

First claim

What is claimed is:

1. An interposer substrate, comprising:
a dielectric layer including a first surface and a second surface opposite to the first surface, wherein the dielectric layer is formed of a same material throughout the dielectric layer;
a first circuit pattern embedded in the dielectric layer and disposed adjacent to the first surface of the dielectric layer, wherein the first circuit pattern includes a first trace;
a second circuit pattern embedded in the dielectric layer and disposed adjacent to the second surface of the dielectric layer;
a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer includes a middle trace, and a width of the middle trace is greater than a width of the first trace;
a first conductive via connecting the first circuit pattern to the middle patterned conductive layer, wherein the first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, and a width of the first conductive via decreases from the first end to the second end; and
a second conductive via connecting the second circuit pattern to the middle patterned conductive layer, wherein the second conductive via includes a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, and a width of the second conductive via decreases from the third end to the fourth end.

2. The interposer substrate according to claim 1 , wherein the second circuit pattern includes a second trace, and a width of the second trace is greater than the width of the middle trace.

3. The interposer substrate according to claim 1 , wherein the second circuit pattern includes a second trace, and a width of the second trace is greater than the width of the first trace.

4. The interposer substrate according to claim 1 , wherein the dielectric layer includes two dielectric sub-layers.

5. The interposer substrate according to claim 1 , wherein the first conductive via and the second conductive via are substantially plane-symmetric with respect to a plane defined by the middle patterned conductive layer.

6. The interposer substrate according to claim 1 , wherein the first circuit pattern includes a first via pad, the second circuit pattern includes a second via pad, the middle patterned conductive layer includes a middle via pad, the first conductive via is connected to the first circuit pattern at the first via pad and is connected to the middle patterned conductive layer at the middle via pad, the second conductive via is connected to the second circuit pattern at the second via pad and is connected to the middle patterned conductive layer at the middle via pad, and a width of the middle via pad is less than or equal to a width of the first via pad or a width of the second via pad.

7. The interposer substrate according to claim 6 , wherein the middle via pad comprises a top surface and a bottom surface, and the top surface and the bottom surface of the middle via pad are each substantially planar.

8. The interposer substrate according to claim 1 , wherein the first circuit pattern is recessed from the first surface of the dielectric layer, and the second circuit pattern is recessed from the second surface of the dielectric layer.

9. The interposer substrate according to claim 1 , wherein the middle patterned conductive layer is single layered.

10. A package structure, comprising:
a base substrate;
an interposer substrate disposed over the base substrate and including:
a dielectric layer including a first surface and a second surface opposite to the first surface, wherein the dielectric layer is formed of a same material throughout the dielectric layer;
a first circuit pattern embedded in the dielectric layer and disposed adjacent to the first surface of the dielectric layer, wherein the first circuit pattern includes first traces;
a second circuit pattern embedded in the dielectric layer and disposed adjacent to the second surface of the dielectric layer;
a middle patterned conductive layer disposed within the dielectric layer and between the first circuit pattern and the second circuit pattern, wherein the middle patterned conductive layer includes middle traces, and a pitch of the middle traces is greater than a pitch of the first traces;
a first conductive via connecting the first circuit pattern to the middle patterned conductive layer, wherein the first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, and a width of the first conductive via at the first end is greater than a width of the first conductive via at the second end; and
a second conductive via connecting the second circuit pattern to the middle patterned conductive layer, wherein the second conductive via includes a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, and a width of the second conductive via at the third end is greater than a width of the second conductive via at the fourth end; and

an encapsulation layer disposed over the base substrate, wherein the encapsulation layer encapsulates the interposer substrate.

11. The package structure according to claim 10 , wherein the second circuit pattern includes second traces, and a pitch of the second traces is greater than the pitch of the middle traces.

12. The package structure according to claim 10 , wherein the second circuit pattern includes second traces, and a pitch of the second traces is greater than the pitch of the first traces.

13. The package structure according to claim 10 , wherein the first circuit pattern includes a first via pad, the second circuit pattern includes a second via pad, the middle patterned conductive layer includes a middle via pad, the first conductive via is connected to the first circuit pattern at the first via pad and is connected to the middle patterned conductive layer at the middle via pad, the second conductive via is connected to the second circuit pattern at the second via pad and is connected to the middle patterned conductive layer at the middle via pad, and a width of the middle via pad is less than or equal to a width of the first via pad or a width of the second via pad.

14. The package structure according to claim 13 , wherein the middle via pad comprises a top surface and a bottom surface, and the top surface and the bottom surface of the middle via pad are each substantially planar.

15. The package structure according to claim 10 , further comprising a semiconductor device disposed over the interposer substrate and adjacent to the first circuit pattern, wherein the interposer substrate electrically connects the semiconductor device to the base substrate, and the encapsulation layer encapsulates the semiconductor device.

16. The package structure according to claim 10 , wherein the first circuit pattern is recessed from the first surface of the dielectric layer, and the second circuit pattern is recessed from the second surface of the dielectric layer.

17. The package structure according to claim 10 , wherein a line width of the first circuit pattern is in a range from 2 μm to 10 μm.

18. The package structure according to claim 10 , wherein the first conductive via and the second conductive via are substantially plane-symmetric with respect to a plane defined by the middle patterned conductive la

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Lee Chih-Cheng
• Su Yuan-Chang

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W46/607

  Located on parts of packages, e.g. on encapsulations or on package substrates · CPC title

• H10W46/301

  for alignment · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title