Integrated circuit device

Patent metadata

Field	Value
Publication number	US-12114504-B2
Application number	US-202117321747-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Aug 13, 2020
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

An integrated circuit device includes a substrate, a peripheral circuit structure disposed on the substrate, the peripheral circuit structure including a peripheral circuit and a lower wiring connected to the peripheral circuit, a conductive plate covering a portion of the peripheral circuit structure, a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, the cell array structure including a memory cell array and an insulation layer surrounding the memory cell array, a through hole via passing through the insulation layer in a direction vertical to a top surface of the substrate to be connected to the lower wiring, and an etch guide member disposed in the insulation layer at the same level as the conductive plate to contact a portion of the through hole via.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a substrate;
a peripheral circuit structure disposed on the substrate, wherein the peripheral circuit structure includes a peripheral circuit and a lower wiring connected to the peripheral circuit;
a conductive plate covering a portion of the peripheral circuit structure;
a cell array structure disposed on the peripheral circuit structure with the conductive plate therebetween, wherein the cell array structure includes a memory cell array and an insulation layer surrounding the memory cell array;
a through hole via passing through the insulation layer, wherein the through hole via connects to the lower wiring and extends in a direction vertical to a top surface of the substrate; and
an etch guide member disposed outside of the conductive plate in the insulation layer at the same level as the conductive plate, wherein:
wherein the conductive plate is configured to transfer a common source voltage to the memory cell array,
the through hole via is disposed between the etch guide member and the conductive plate and contacts the etch guide member on a first side of the through hole via, and
wherein the through hole via contacts the insulation layer on a second side of the through hole via opposite to the first side.

2. The integrated circuit device of claim 1 , wherein a groove is formed on an edge of the etch guide member, and
wherein a sidewall of the through hole via contacting the etch guide member is formed in a staircase shape filled into the groove.

3. The integrated circuit device of claim 2 , wherein the etch guide member is disposed at one side of the through hole via.

4. The integrated circuit device of claim 1 , wherein the memory cell array is disposed on the conductive plate, and
wherein the memory cell array is not disposed on the etch guide member.

5. The integrated circuit device of claim 1 , wherein the lower wiring comprises a plurality of wiring layers, and
wherein a lowermost surface of the through hole via contacts a top surface of an uppermost layer of the plurality of wiring layers.

6. The integrated circuit device of claim 5 , further comprising an upper wiring disposed at a level that is higher than a level of the memory cell array,
wherein an uppermost surface of the through hole via is connected to the upper wiring, and
wherein a width of the uppermost surface of the through hole via is greater than a width of the lowermost surface of the through hole via.

7. The integrated circuit device of claim 1 , wherein the etch guide member and the insulation layer comprise different materials, and
wherein the etch guide member and the conductive plate comprise the same material.

8. The integrated circuit device of claim 7 , wherein a material of the etch guide member has an etch selectivity with respect to a material of the insulation layer.

9. The integrated circuit device of claim 7 , wherein the etch guide member and the conductive plate comprise doped polysilicon, and
wherein a maximum thickness of the etch guide member is the same as a maximum thickness of the conductive plate.

10. An integrated circuit device comprising:
a substrate;
a peripheral circuit structure disposed on the substrate, wherein the peripheral circuit structure includes a peripheral circuit and a lower wiring connected to the peripheral circuit;
a cell array structure overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure includes a memory stack that includes a plurality of gate lines stacked in the vertical direction and a channel structure passing through the plurality of gate lines in the vertical direction;
a conductive plate disposed between the peripheral circuit structure and the cell array structure;
a through hole via passing through the cell array structure wherein the through hole via extends to an inner portion of the peripheral circuit structure to be connected to the lower wiring, outside the conductive plate; and
an etch guide member disposed outside the conductive plate at the same level as the conductive plate, wherein:
wherein the conductive plate is configured to transfer a common source voltage to the memory stack,
the etch guide member has the same thickness as a thickness of the conductive plate, and includes the same material as the conductive plate, with the through hole via therebetween;
wherein the etch guide member penetrates into the through hole via in a horizontal direction; and
wherein the through hole via is disposed between the etch guide member and the conductive plate and contacts the etch guide member on a first side of the through hole via and wherein the through hole via contacts the insulation layer on a second side of the through hole via opposite to the first side.

11. The integrated circuit device of claim 10 , wherein the through hole via is electrically connected to an upper wiring disposed at a vertical level that is higher than a vertical level of the channel structure.

12. The integrated circuit device of claim 10 , wherein a portion of the etch guide member comprises a portion damaged by dry etching in a direction contacting the through hole via.

13. The integrated circuit device of claim 10 , wherein the through hole via has a tapered shape where a width of the through hole via narrows toward the substrate, and
wherein the width of the through hole via narrows discontinuously at a point contacting the etch guide member.

14. An integrated circuit device comprising:
a substrate;
a peripheral circuit structure disposed on the substrate, wherein the peripheral circuit structure includes a peripheral circuit and a plurality of lower wiring layers connected to the peripheral circuit;
a cell array structure overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure includes a memory stack that includes a plurality of gate lines stacked and a channel structure passing through the plurality of gate lines in the vertical direction, wherein the cell array structure further includes an insulation layer surrounding the memory stack, and a plurality of upper wiring layers disposed on the channel structure;
a plate common source line disposed between the peripheral circuit structure and the cell array structure;
a through hole via passing through the insulation layer, wherein the through hole via extends to an inner portion of the peripheral circuit structure to be connected up to an uppermost layer of the plurality of lower wiring layers from a lowermost layer of the plurality of upper wiring layers; and
an etch guide member disposed outside the plate common source line, wherein:
the etch guide member is disposed at the same level as the plate common source line, has the same thickness as a thickness of the plate common source line, and includes the same material as a material of the plate common source line, and
wherein the through hole via is disposed between the etch guide member and the conductive plate and contacts the etch guide member on a first side of the through hole via and wherein the through hole via contacts the insulation layer on a second side of the through hole via opposite to the first side.

15. The integrated circuit device of claim 14 , wherein the etch guide member comprises doped polysilicon, and
wherein a material of the etch guide member has an etch selectivity with respect to a material of the insulation layer.

16. The integrated circuit device of claim 14 , wherein the etch guide member is spaced apart from an uppermost layer of the plurali

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seungyoon
• Sim Jaeryong
• Han Jeehoon

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title