Three-dimensional memory device containing capacitor pillars and methods of making the same

Patent metadata

Field	Value
Publication number	US-10629675-B1
Application number	US-201816210306-A
Country	US
Kind code	B1
Filing date	Dec 5, 2018
Priority date	Dec 5, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A semiconductor structure can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and capacitor pillar structures vertically extending through the first alternating stack. Each of the capacitor pillar structures can include a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric. A first electrode layer of a capacitor includes the semiconductor material portions, and a second electrode layer of the capacitor includes the electrically conductive layers. Alternatively or additionally, a first dielectric fill material portion can extend through the alternating stack and can include a plurality of capacitor via cavities. A capacitor can be provided within the plurality of capacitor via cavities.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a first alternating stack of insulating strips and electrically conductive strips located over a substrate; and
capacitor pillar structures vertically extending through the first alternating stack, wherein each of the capacitor pillar structures comprises a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric,
wherein:
the semiconductor material portions are electrically connected to provide a first electrode layer of a capacitor;
the electrically conductive strips are electrically connected to provide a second electrode layer of the capacitor; and
the node dielectrics collectively constitute an insulating dielectric between the first electrode layer and the second electrode layer of the capacitor.

2. The semiconductor structure of claim 1 , further comprising:
a second alternating stack of insulating layers and electrically conductive layers located over the substrate; and
memory stack structures vertically extending through the second alternating stack, wherein:
the insulating layers have a same material composition as the insulating strips within the first alternating stack; and
the electrically conductive layers have a same material composition as the electrically conductive strips within the first alternating stack.

3. The semiconductor structure of claim 2 , wherein:
each insulating layer in the second alternating stack is located at a same vertical distance from the substrate as a corresponding one of the insulating strips within the first alternating stack; and
each electrically conductive layer in the second alternating stack is located at a same vertical distance from the substrate as a corresponding one of the electrically conductive strips within the first alternating stack.

4. The semiconductor structure of claim 2 , wherein:
each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel;
each of the memory films includes a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer; and
each of the node dielectrics includes a first dielectric layer having a same composition and a same thickness as the blocking dielectric layer, a second dielectric layer having a same composition and a same thickness as the charge storage layer, and a third dielectric layer having a same composition and a same thickness as the tunneling dielectric layer.

5. The semiconductor structure of claim 2 , further comprising a source contact layer underlying the second alternating stack and overlying the substrate, comprising a doped semiconductor material, and contacting sidewalls of the semiconductor material portions and electrically connecting the semiconductor material portions.

6. A semiconductor structure comprising:
an alternating stack of insulating layers and electrically conductive layers and overlying a substrate;
a first dielectric fill material portion vertically extending through the alternating stack and including a plurality of capacitor via cavities therein, wherein each of the plurality of capacitor via cavities vertically extend through the alternating stack;
a first electrode layer continuously extending into the plurality of capacitor via cavities and contacting sidewalls of the plurality of capacitor via cavities;
a node dielectric continuously extending into the plurality of capacitor via cavities and overlying the first electrode layer; and
a second electrode layer continuously extending into the plurality of capacitor via cavities and overlying the node dielectric,
wherein the first electrode layer, the node dielectric, and the second electrode layer collectively constitute a capacitor.

7. The semiconductor structure of claim 6 , further comprising:
at least one dielectric material layer located between the alternating stack and the substrate; and
metal interconnect structures positioned within the at least one dielectric material layer,
wherein bottom surfaces of the first electrode layer located at bottom regions of the capacitor via cavities contacts a top surface of one of the metal interconnect structures.

8. The semiconductor structure of claim 7 , further comprising:
a second dielectric fill material portion vertically extending through the alternating stack and including at least one contact via cavity therein; and
at least one contact via structure located within the at least one contact via cavity and contacting a top surface of another one of the metal interconnect structures.

9. The semiconductor structure of claim 7 , further comprising:
a semiconductor device located within, or on a top surface of, the substrate;
an electrically conductive path comprising a subset of the metal interconnect structures and electrically connecting a node of the semiconductor device and the first electrode layer; and
at least one upper level metal interconnect structure that provides a conductive path to the second electrode layer.

10. The semiconductor structure of claim 6 , further comprising memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel.

11. A method of forming a three-dimensional semiconductor device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming capacitor openings through a first region of the alternating stack;
forming capacitor pillar structures in the capacitor openings, wherein each of the capacitor pillar structures comprises a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric;
forming a conductive structure that electrically connects the semiconductor material portions, the conductive structure and the semiconductor material portions constituting a first electrode layer of a capacitor; and
replacing the sacrificial material layers with conductive material portions, the conductive material portions including electrically conductive layers that are electrically connected and laterally surround the node dielectrics to constitute a second electrode layer of the capacitor.

12. The method of claim 11 , further comprising:
forming memory openings through the alternating stack simultaneously with formation of the capacitor openings; and
forming memory stack structures in the memory openings simultaneously with formation of the capacitor pillar structures, wherein each of the memory stack structures comprises a respective memory film and a respective vertical semiconductor channel.

13. The method of claim 12 , wherein:
the conductive material portions comprise electrically conductive layers that are electrically isolated and laterally surround the memory stack structures; and
the memory stack structures and the electrically conductive layers comprise vertical NAND strings.

14. The method of claim 12 , further comprising:
forming a continuous blocking dielectric layer on sidewalls of the capacitor openings and the memory openings;
forming a continuous charge storage layer on the continuous blocking dielectric layer;
forming a continuous tunneling dielectric layer on the continuous charge storage layer; and
removing portions of the continuous tunneling dielectric layer, the continuous charge storage layer, and the continuous blocking dielectric layer, wherein remaining portions of the continuous tunneling dielectric layer, the continuous charge storage layer, and the continuous blocking dielectric l

Assignees

• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Chibvongodze Hardwell

Classifications

• H01L21/0217

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L29/40114

  Electricity · mapped topic