Memory device having cell over periphery (COP) structure, memory package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9799672-B2
Application number	US-201615015120-A
Country	US
Kind code	B2
Filing date	Feb 3, 2016
Priority date	Apr 15, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A memory device includes a semiconductor substrate, a peripheral circuit formed on a top surface of the semiconductor substrate, a lower insulation layer covering the peripheral circuit, a base layer formed on the lower insulation layer, a memory cell array formed on the base layer, an upper insulation layer covering the memory cell array and a plurality of input-output pads formed on a bottom surface of the semiconductor substrate. At least one of the input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction. The sizes of the memory device and the memory package including the memory device may be reduced through the COP structure and efficient arrangement of the input-output pads.

First claim

What is claimed is:

1. A memory device comprising:
a semiconductor substrate having a top surface and a bottom surface;
a peripheral circuit formed on the top surface of the semiconductor substrate;
a lower insulation layer covering the peripheral circuit;
a base layer formed on the lower insulation layer;
a memory cell array formed on the base layer;
an upper insulation layer covering the memory cell array;
a plurality of input-output pads formed on the bottom surface of the semiconductor substrate, wherein at least one of the plurality of input-output pads is disposed to be overlapped with a portion of the memory cell array in a vertical direction, and wherein the memory cell array includes a plurality of vertical NAND flash memory cells; and
a plurality of through-substrate vias penetrating the semiconductor substrate and a portion of the lower insulation layer configured to connect the input-output pads with input-output pad of another semiconductor memory device.

2. The memory device of claim 1 ,
wherein the memory cell array includes:
a plurality of channels extending in the vertical direction; and
a plurality of gate lines surrounding outer sidewalls of the channels,
wherein the gate lines are stacked in the vertical direction and spaced apart from each other, and
wherein at least one of the plurality of input-output pads is disposed to be overlapped with at least one of the plurality of channels of the memory cell array in the vertical direction.

3. The memory device of claim 1 , wherein at least one of the through-substrate vias is disposed to be overlapped with the portion of the memory cell array in the vertical direction.

4. The memory device of claim 1 , wherein the plurality of input-output pads are arranged near one side of the semiconductor substrate.

5. The memory device of claim 1 , wherein the plurality of through-substrate vias connect the plurality of input-output pads with a plurality of lower wiring patterns in the lower insulation layer.

6. The memory device of claim 5 , wherein the plurality of through-substrate vias are formed using the plurality of lower wiring patterns as an etch stop layer, after the plurality of lower wiring patterns are formed.

7. The memory device of claim 1 , wherein the base layer includes polysilicon or single crystalline silicon.

8. The memory device of claim 7 , wherein the base layer is divided into a plurality of base layer patterns and each of the plurality of base layer patterns serves as a p-type well.

9. A memory package comprising:
a base substrate; and
a plurality of memory chips stacked on the base substrate, each of the plurality of memory chips comprising:
a semiconductor substrate having a top surface and a bottom surface;
a peripheral circuit formed on the top surface of the semiconductor substrate;
a lower insulation layer covering the peripheral circuit;
a base layer formed on the lower insulation layer;
a memory cell array formed on the base layer;
an upper insulation layer covering the memory cell array; and
a plurality of input-output pads formed on the bottom surface of the semiconductor substrate,

wherein the memory cell array includes:
a plurality of channels extending in a vertical direction; and
a plurality of gate lines surrounding outer sidewalls of the plurality of channels, the plurality of gate lines being stacked in the vertical direction and spaced apart from each other, and
wherein at least one of the plurality of input-output pads is disposed to be overlapped with at least one of the plurality of channels of the memory cell array in the vertical direction.

10. The memory package of claim 9 ,
wherein the plurality of memory chips are stacked on the base substrate in an upside-down state such that the bottom surface of the semiconductor substrate of each of the plurality of memory chips faces upwards.

11. The memory package of claim 10 ,
wherein, with respect to each memory chip, the plurality of input-output pads are arranged near one side of the bottom surface of the semiconductor substrate.

12. The memory package of claim 11 ,
wherein the plurality of memory chips are stacked in a step shape such that the plurality of input-output pads of each memory chip are exposed.

13. The memory package of claim 12 , wherein the plurality of memory chips are electrically connected to the base substrate through a plurality of bonding wires.

Assignees

• SON Jae-Ick
• Kim Sung-Hoon
• Samsung Electronics Co Ltd

Inventors

• SON Jae-Ick
• Kim Sung-Hoon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/00

  Package configurations · CPC title

• H01L27/11529

  Electricity · mapped topic