Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10446570-B2
Application number	US-201815988346-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	Nov 8, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element;
a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate;
a second dielectric layer covering the memory cell array;
a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and
at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

2. The semiconductor memory device according to claim 1 , further comprising:
an etch stopper coupled to a lower end of the at least one dummy contact.

3. The semiconductor memory device according to claim 2 , wherein the etch stopper is disposed over a top surface of the first dielectric layer and is coplanar with the second substrate.

4. The semiconductor memory device according to claim 2 , wherein the etch stopper is formed of a material which has a different etching selectivity from the second dielectric layer.

5. The semiconductor memory device according to claim 4 , wherein the second dielectric layer comprises a silicon oxide layer, and the etch stopper comprises at least one of a silicon nitride film and a polycrystalline silicon layer.

6. The semiconductor memory device according to claim 2 , wherein the etch stopper is formed of the same material as the second substrate.

7. The semiconductor memory device according to claim 3 , wherein the etch stopper includes an opening through which the contact passes.

8. The semiconductor memory device according to claim 1 , wherein the at least one dummy contact has the same shape as the contact when viewed from the top.

9. The semiconductor memory device according to claim 1 , wherein the contact and the at least one dummy contact are formed of the same material.

10. The semiconductor memory device according to claim 1 , wherein the contact has a circular shape when viewed from the top, and the at least one dummy contact has a bar shape when viewed from the top.

11. The semiconductor memory device according to claim 1 , wherein the contact has a circular shape when viewed from the top, and the at least one dummy contact comprises a plurality of dummy contacts arranged in a shape which surrounds the contact, when viewed from the top.

12. The semiconductor memory device according to claim 1 , wherein the at least one dummy contact comprises a plurality of dummy contacts arranged in a discontinuous frame shape surrounding the contact, when viewed from the top.

13. The semiconductor memory device according to claim 1 , wherein the at least one dummy contact comprises a dummy contact having a continuous frame shape surrounding the contact, when viewed from the top.

14. A semiconductor memory device comprising:
a peripheral circuit region including a first substrate, peripheral circuit elements which are disposed over the first substrate, a first dielectric layer which covers the peripheral circuit elements and a bottom wiring line which is disposed in the first dielectric layer and is electrically coupled to the peripheral circuit elements;
a cell region including a second substrate and an etch stopper which are disposed over the first dielectric layer, channel structures which extend in a first direction perpendicular to a top surface of the second substrate, a plurality of gate electrode layers and a plurality of interlayer dielectric layers which are alternately stacked over the second substrate to be adjacent to the channel structures and a second dielectric layer which covers the gate electrode layers;
a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in the first direction; and
a plurality of dummy contacts coupled to the etch stopper by passing through the second dielectric layer in the first direction, and disposed adjacent to the contact.

15. The semiconductor memory device according to claim 14 , wherein the dummy contacts are arranged in a pattern which surrounds the contact.

16. The semiconductor memory device according to claim 14 , wherein the etch stopper includes an opening through which the contact passes.

17. The semiconductor memory device according to claim 16 , wherein the dummy contacts are arranged along edges of the opening.

18. The semiconductor memory device according to claim 14 ,
wherein the contact and the dummy contacts are formed of the same material.

19. A semiconductor memory device comprising:
a first substrate;
a peripheral circuit element disposed at least partially over the first substrate;
a first dielectric layer covering the peripheral circuit element;
a wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element;
a second substrate disposed over the first dielectric layer;
a second dielectric layer disposed over the second substrate;
a contact coupled to the wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and
at least one dummy contact disposed adjacent to the contact in the second dielectric layer.

20. The semiconductor memory device according to claim 19 , further comprising:
a memory cell array disposed over the second substrate inside the second dielectric layer, and
an etch stopper coupled to a lower end of the at least one dummy contact.

Assignees

• Sk Hynix Inc

Inventors

• Lee Go-Hyun
• Kim Jae-Taek
• Kim Jun-Youp
• Son Chang-Man

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/10897

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic