Through-memory-level via structures for a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-10381371-B2
Application number	US-201615269112-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Dec 22, 2015
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a memory-level assembly located over a semiconductor substrate and including at least one alternating stack and memory stack structures vertically extending through the at least one alternating stack, wherein the at least one alternating stack includes alternating layers of respective insulating layers and respective electrically conductive layers;
a plurality of laterally-elongated contact via structures that vertically extend through the memory-level assembly, laterally extend along a first horizontal direction, and laterally divides the at least one alternating stack into a plurality of laterally spaced-apart blocks, wherein the plurality of blocks comprises a set of three neighboring blocks including, in order, a first block, a second block, and third block arranged along a second horizontal direction that is perpendicular to the first horizontal direction;
a through-memory-level via region located adjacent to a lengthwise end of the second block and between a staircase region of the first block and a staircase region of the third block, wherein the through-memory-level via region comprises vertically extending through-memory-level via structures embedded in a dielectric fill material portion; and
word line switch devices located on or over the substrate in the through-memory-level via region under the vertically extending through-memory-level via structures and the dielectric fill material portion.

2. The semiconductor structure of claim 1 , further comprising:
at least one lower level dielectric layer overlying the semiconductor substrate; and
lower level metal interconnect structures electrically shorted to nodes of the word line switch devices and embedded in the at least one lower level dielectric layer, wherein the through-memory-level via structures contact the lower level metal interconnect structures.

3. The semiconductor structure of claim 2 , wherein:
each of the memory stack structures comprises a vertical stack of memory elements located at each level of the electrically conductive layers;
the electrically conductive layers comprise word lines for the memory elements; and
the word line switch devices are configured to control a bias voltage to respective word lines.

4. The semiconductor structure of claim 3 , further comprising:
word line contact via structures extending through a retro-stepped dielectric material portion that overlies the staircase regions of the first and third blocks and contacting the word lines; and
upper level metal interconnect structures electrically shorting respective pairs of a word line contact via structure and a through-memory-level via structure, wherein the upper level metal interconnect structures overly the memory-level assembly, and straddle the second block and one of the first and third blocks.

5. The semiconductor structure of claim 4 , wherein each of the through-memory-level via structures contacts a respective overlying upper level metal interconnect structure.

6. The semiconductor structure of claim 1 , wherein:
the dielectric fill material portion comprises substantially vertical sidewalls that extend through the memory-level assembly;
each staircase region of the first and third blocks includes terraces in which each underlying electrically conductive layer extends farther along the first horizontal direction than any overlying electrically conductive layer within the memory-level assembly; and
each of the memory stack structures comprises a memory film and a vertical semiconductor channel that is adjoined to a respective horizontal channel within the substrate underlying the memory-level assembly.

7. The semiconductor structure of claim 6 , further comprising a plurality of bit lines which are electrically coupled to drain regions of the memory stack structures.

8. The semiconductor structure of claim 1 , wherein:
the memory stack structures comprise memory elements of a vertical NAND device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the semiconductor substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising the word line driver circuit and a bit line driver circuit for the memory device; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the semiconductor substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

9. A three dimensional NAND memory device, comprising:
word line driver devices located on or over a substrate;
an alternating stack of word lines and insulating layers located over the word line driver devices;
a plurality of memory stack structures extending through the alternating stack, each memory stack structure comprising a memory film and a vertical semiconductor channel; and
through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices;
wherein the through-memory-level via structures extend through a dielectric fill material portion located between a staircase region of the first memory block and a staircase region of another memory block, and the word line driver devices are located wherein under the through-memory-level via structures and the dielectric fill material portion.

10. The device of claim 9 , further comprising:
word line contact via structures extending through a dielectric material portion that overlies the staircase regions of the first memory block and contacting the word lines in the first memory block; and
upper level metal interconnect structures electrically shorting respective pairs of a word line contact via structure and a through-memory-level via structure, wherein the upper level metal interconnect structures overly the alternating stack, and straddle the first memory block and the dielectric fill material portion.

Assignees

• Sandisk Technologies Llc

Inventors

• Ogawa Hiroyuki
• Toyama Fumiaki
• Mizutani Yuki

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title