Subtractively patterned interconnect structures for integrated circuits

Patent metadata

Field	Value
Publication number	US-12027458-B2
Application number	US-202217841551-A
Country	US
Kind code	B2
Filing date	Jun 15, 2022
Priority date	Nov 2, 2020
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

First claim

What is claimed is:

1. An integrated circuit (IC) structure comprising:
a plurality of transistors; and
an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
a via and a dielectric material adjacent to the via;
a line in contact with the via, wherein the line extends over the dielectric material, and a top width of the line is smaller than a bottom width of the line; and
a barrier material on a sidewall of the line and between the sidewall of the line and the dielectric material, wherein the barrier material comprises graphene or a metal chalcogenide, and wherein the barrier material is substantially absent from a sidewall of the via.

2. The IC structure of claim 1 , wherein the barrier material is also on a top of the line.

3. The IC structure of claim 1 , wherein the line comprises at least one of Cu, W, Ru, Co, Mo, W, Jr, Rh, or Pt.

4. The IC structure of claim 3 , wherein the barrier material comprises the Cu, W, Ru, Co, Mo, W, Jr, Rh, or Pt and at least one chalcogen.

5. The IC structure of claim 1 , wherein the via has a different composition than the line.

6. The IC structure of claim 1 , further comprising a bottom barrier material, and wherein the bottom barrier material is absent from between the via and the line.

7. The IC structure of claim 6 , wherein the bottom barrier material comprises a metal chalcogenide, a metal oxide, a metallic compound comprising predominantly one of Ta, Co, or Ru, or a dielectric comprising silicon and at least one of nitrogen, or oxygen.

8. The IC structure of claim 7 , wherein the barrier material on the sidewall comprises graphene.

9. The IC structure of claim 1 , further comprising:
a row of first interconnect features, wherein a first end space between an adjacent pair of the first interconnect features has a first misregistration in a first lateral dimension relative to an underlying feature of the IC structure; and
a row of second interconnect features coplanar with the first interconnect features, wherein individual ones of the rows of second interconnect features are between, and parallel with, individual ones of the rows of first interconnect features, and a second end space between an adjacent pair of the second interconnect features has a second misregistration in the first lateral dimension relative to the underlying feature of the IC structure.

10. The IC structure of claim 9 , further comprising:
a first cap material over the first interconnect features, wherein the first cap material has a first composition; and
a second cap material over the second interconnect features, wherein the second cap material has a second composition, different than the first composition.

11. An IC structure, wherein the IC structure comprises:
a plurality of transistors; and
an interconnect structure coupled to the transistors, wherein the interconnect structure comprises:
a via and a dielectric material adjacent to the via;
a line in contact with the via, wherein the line extends over the dielectric material, and a top width of the line is smaller than a bottom width of the line; and
a barrier material on a sidewall of the line and between the sidewall of the line and the dielectric material, wherein the barrier material comprises a metal and a chalcogen.

12. The IC structure of claim 11 , wherein:
the line comprises at least one of Cu, W, Ru, Co, Mo, W, Jr, Rh, or Pt; and
the barrier material comprises the Cu, W, Ru, Co, Mo, W, Jr, Rh, or Pt and at least one chalcogen.

13. The IC structure of claim 11 , wherein the barrier material is also on a top of the line.

14. A method of forming an integrated circuit (IC) interconnect structure, the method comprising:
depositing a metal over a substrate comprising a plurality of transistors and interconnect vias;
forming interconnect lines coupled through the interconnect vias to the transistors by etching a portion of the metal;
forming at least one of graphene or a metal chalcogenide in contact with a sidewall of the interconnect lines, but absent from the interconnect vias; and
depositing a dielectric material over the interconnect features.

15. The method of claim 14 , wherein etching the metal comprises performing an etch process that narrows a top transverse width of individual ones of the interconnect lines relative to a bottom transverse width of corresponding ones of the interconnect lines.

16. The method of claim 14 , wherein forming the graphene or a metal chalcogenide further comprises doping the metal with a chalcogen.

17. The method of claim 14 , further comprising depositing a bottom barrier material prior to depositing the metal, and depositing of the metal in physical contact with the bottom barrier material.

18. The method of claim 17 , wherein depositing the bottom barrier material forms less bottom barrier material on a surface of the interconnect via than on a dielectric material surface adjacent to the interconnect via.

19. The method of claim 18 , wherein depositing the bottom barrier material further comprises an area selective deposition process that forms the bottom barrier material on dielectric material surfaces at a higher rate than over metallic material surfaces, and wherein the area selective deposition process comprises an atomic layer deposition cycle further comprising reacting metallic material surfaces with an inhibitor, reacting dielectric surfaces with a metallic precursor, and reacting the metallic precursor with a co-reactant to form metallic material.

20. The method of claim 19 , wherein the metallic material comprises Ta and N.

Assignees

• Intel Corp

Inventors

• Lin Kevin
• Sato Noriyuki
• Tronic Tristan
• Christenson Michael
• Jezewski Christopher
• Chen Jiun-Ruey
• Blackwell James M
• Metz Matthew
• Reshotko Miriam
• Kabir Nafees
• Bielefeld Jeffery
• Chandhok Manish
• Yoo Hui Jae
• Karpov Elijah
• Naylor Carl
• Chebiam Ramanan

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title