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Method of creating a maskless air gap in back end interconnects with double self-aligned vias
US8975138B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975138-B2 |
| Application number | US-201313931219-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 28, 2013 |
| Priority date | Jun 28, 2013 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
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A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: patterning a first interconnect material on a device layer of an integrated circuit substrate, the first interconnect material comprising length and width dimensions selected for a wiring line; patterning a thickness dimension of the first interconnect material into a thickness dimension for a first wiring line with one or more vias extending from the wiring line; introducing a dielectric material on the first interconnect material s…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8975138B2 cover?
- A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on…
- Who is the assignee on this patent?
- Chandhok Manish, Yoo Hui Jae, Borodovsky Yan A, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/495. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).