Integrated circuit device including multiple via connectors and a metal structure having a ladder shape

Patent metadata

Field	Value
Publication number	US-2016233159-A1
Application number	US-201514855939-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Feb 10, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

In a particular aspect, an apparatus includes a first via of an integrated circuit. The apparatus includes a second via of the integrated circuit. The apparatus includes a first via connector coupled to the first via. The apparatus includes a second via connector coupled to the second via. The apparatus further includes a metal structure separated from and encircling the first via connector and the second via connector.

First claim

What is claimed is:

1 . An apparatus comprising:
a first via of an integrated circuit; a second via of the integrated circuit; a first via connector coupled to the first via; a second via connector coupled to the second via; and a metal structure separated from and encircling the first via connector and the second via connector.

2 . The apparatus of claim 1 , wherein the integrated circuit comprises a memory.

3 . The apparatus of claim 2 , wherein the memory comprises a static random access memory (SRAM) device.

4 . The apparatus of claim 1 , wherein the first via connector, the second via connector, and the metal structure are included in a first metal layer of the integrated circuit, and wherein the first metal layer is disposed above a layer containing at least one circuit element.

5 . The apparatus of claim 1 , wherein the first via connector comprises a word line connection pad coupled to a word line of a memory cell.

6 . The apparatus of claim 1 , wherein the second via connector comprises a word line connection pad coupled to a word line of a memory cell.

7 . The apparatus of claim 1 , wherein the metal structure has a ladder shape.

8 . The apparatus of claim 7 , wherein the metal structure is coupled to a voltage source or to ground.

9 . The apparatus of claim 1 , wherein the metal structure comprises a voltage source connection.

10 . The apparatus of claim 1 , wherein the first via couples a gate of a transistor to the first via connector, and wherein a third via couples the first via connector to a word line.

11 . The apparatus of claim 10 , wherein the gate is included in a first layer of the integrated circuit, wherein the first via connector, the second via connector, and the metal structure are included in a first metal layer of the integrated circuit, and wherein the word line is included in a second metal layer of the integrated circuit.

12 . The apparatus of claim 10 , wherein the integrated circuit comprises a static random access memory (SRAM) device, and wherein the transistor and the word line are included in a six transistor (6T) memory cell of the SRAM device.

13 . A method of fabricating an integrated circuit device comprising:
forming a first layer that includes a circuit element; and forming a second layer that includes a first via connector, a second via connector, and a metal structure, the metal structure separated from and encircling the first via connector and the second via connector.

14 . The method of claim 13 , further comprising:
forming multiple mandrel structures after forming the first layer; and depositing spacing material proximate to each of the multiple mandrel structures to form spacers.

15 . The method of claim 14 , wherein the multiple mandrel structures include a mandrel structure having a ladder shape.

16 . The method of claim 14 , wherein the multiple mandrel structures include a first group of non-contiguous mandrel elements aligned in a first alignment direction and a second group of non-contiguous mandrel elements aligned in the first alignment direction.

17 . The method of claim 16 , wherein the first alignment direction is horizontal.

18 . The method of claim 16 , wherein the multiple mandrel structures include a third unitary mandrel proximate to the first group of non-contiguous mandrel elements.

19 . The method of claim 14 , further comprising:
removing the multiple mandrel structures; performing a hard mask etch process to form trenches around the spacers; and removing the spacers.

20 . The method of claim 19 , wherein the multiple mandrel structures are removed without performing a cut process using a cut metal pattern.

21 . The method of claim 19 , wherein the spacers are used as a hard mask during the hard mask etch process.

22 . The method of claim 19 , further comprising filling the trenches with metal to form the first via connector, the second via connector, and the metal structure.

23 . The method of claim 22 , further comprising patterning a first via coupled to the circuit element and the first via connector and patterning a second via coupled to a second circuit element of the first layer and the second via connector.

24 . An apparatus comprising:
means for coupling a first group of vias; means for coupling a second group of vias; and means for conducting, the means for conducting separated from and encircling the means for coupling the first group of vias and the means for coupling the second group of vias.

25 . The apparatus of claim 24 , wherein the means for conducting has a ladder shape.

26 . The apparatus of claim 24 , wherein the means for conducting comprises a voltage source connection coupled to a voltage source.

27 . The apparatus of claim 24 , wherein a first via of the first group of vias couples a gate of a transistor to the means for coupling the first group of vias, and wherein a second via couples the means for coupling the first group of vias to a word line.

28 . A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising:
initiating formation of a first layer that includes a first circuit element and a second circuit element; initiating formation of multiple mandrel structures; initiating deposition of spacing material proximate to each of the multiple mandrel structures to form spacers; initiating removal of the multiple mandrel structures; initiating performance of a hard mask etch process to form trenches around the spacers; initiating removal of the spacers; initiating filling of the trenches with metal to produce a first via connector, a second via connector, and a metal structure, the metal structure separated from and encircling the first via connector and the second via connector; and initiating patterning of a first via coupled to the first circuit element and the first via connector and patterning of a second via coupled to the second circuit element and the second via connector.

29 . The non-transitory computer-readable medium of claim 28 , wherein the metal structure has a ladder shape.

30 . The non-transitory computer-readable medium of claim 28 , wherein the multiple mandrel structures are removed without performing a cut process using a cut metal pattern.

Assignees

• Qualcomm Inc

Inventors

• Song Stanley Seungchul
• Mojumder Niladri Narayan
• Yang Da
• Yeap Choh Fei

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D89/10

  Integrated device layouts · CPC title