Selective Deposition of Metal Barrier in Damascene Processes

Patent metadata

Field	Value
Publication number	US-2020105592-A1
Application number	US-201816213622-A
Country	US
Kind code	A1
Filing date	Dec 7, 2018
Priority date	Sep 28, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

First claim

1 . A method of forming an integrated circuit structure, the method comprising:
forming an etch stop layer over a conductive feature; forming a dielectric layer over the etch stop layer; forming an opening in the dielectric layer to reveal the etch stop layer; etching the etch stop layer through the opening using an etchant comprising an inhibitor, wherein an inhibitor film comprising the inhibitor is formed on the conductive feature; depositing a conductive barrier layer extending into the opening; after the conductive barrier layer is deposited, performing a treatment to remove the inhibitor film; and depositing a conductive material to fill a remaining portion of the opening.

2 . The method of claim 1 further comprising, after the etch stop layer is etched, soaking a respective wafer comprising the etch stop layer and the inhibitor film in a chemical solution to increase a thickness of the inhibitor film, wherein during the soaking, the etch stop layer is not etched.

3 . The method of claim 2 , wherein the etchant and the chemical solution comprises a same type of inhibitor.

4 . The method of claim 1 , wherein the treatment comprises a plasma treatment using hydrogen (H 2 ) as a process gas.

5 . The method of claim 1 , wherein the treatment comprises a thermal treatment using hydrogen (H 2 ) as a process gas.

6 . The method of claim 1 , wherein the inhibitor in the etchant comprises Benzotriazole, and the conductive feature comprises copper.

7 . The method of claim 1 , wherein the conductive barrier layer form isolated islands on the inhibitor film.

8 . The method of claim 7 , wherein after the treatment, the isolated islands are in contact with an interface between the conductive feature and the conductive material.

9 . The method of claim 8 , wherein the isolated islands are separated from each other by the conductive material.

10 . A method of forming an integrated circuit structure, the method comprising:
forming an etch stop layer over a conductive feature; forming a dielectric layer over the etch stop layer; forming an opening in the dielectric layer to reveal the etch stop layer; etching the etch stop layer; and selectively depositing a conductive barrier layer extending into the opening, wherein the selective depositing results in the conductive barrier layer to have a first thickness on a sidewall of the dielectric layer, and the conductive barrier layer is at least thinner at a bottom of the opening than on the sidewall of the dielectric layer.

11 . The method of claim 10 , wherein the conductive barrier layer comprises discrete islands at the bottom of the opening.

12 . The method of claim 10 , wherein the conductive barrier layer does not extend to the bottom of the opening.

13 . The method of claim 10 , wherein the etching the etch stop layer results in an inhibitor film to be formed on a top surface of the conductive feature, and the method further comprises:
after the conductive barrier layer is formed, removing the inhibitor film; and depositing a conductive material to fill a remaining portion of the opening.

14 . The method of claim 13 , wherein the removing the inhibitor film comprises a plasma treatment using hydrogen (H 2 ) as a process gas.

15 . The method of claim 13 , wherein the removing the inhibitor film comprises a thermal treatment using hydrogen (H 2 ) as a process gas.

16 . An integrated circuit structure comprising:
a first conductive feature; an etch stop layer over the first conductive feature; a dielectric layer over the etch stop layer; and a second conductive feature extending into the dielectric layer and the etch stop layer, wherein the second conductive feature comprises:
a conductive barrier layer comprising a first portion on sidewalls of the dielectric layer, wherein the first portion forms a continuous layer, and second portions on a top surface of the conductive feature, wherein the second portions are thinner than the first portion; and
a conductive region encircled by the first portions of the conductive barrier layer, wherein the conductive region is over and contacting the second portions of the conductive barrier layer.

17 . The integrated circuit structure of claim 16 , wherein the second portions are discrete islands separated from each other by the conductive region.

18 . The integrated circuit structure of claim 17 , wherein the discrete islands are at, and in contact with, an interface between the first conductive feature and the conductive region.

19 . The integrated circuit structure of claim 16 , wherein the conductive barrier layer comprises TaN.

20 . The integrated circuit structure of claim 16 , wherein the second portions of the conductive barrier layer have a coverage smaller than about 50 percent.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chia-Pang
• Lee Ya-Lien
• Shen Chieh-Yi

Classifications

• H01L23/5226

  Electricity · mapped topic

• H01L21/7681

  Electricity · mapped topic

• H01L23/53238

  Electricity · mapped topic

• H01L21/76844 Primary

  Electricity · mapped topic

• H01L21/76879

  Electricity · mapped topic