Planar slab vias for integrated circuit interconnects

Patent metadata

Field	Value
Publication number	US-11239156-B2
Application number	US-202016824366-A
Country	US
Kind code	B2
Filing date	Mar 19, 2020
Priority date	Mar 19, 2020
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

Integrated circuitry comprising devices electrically coupled through a plurality of interconnect levels in which lines of a first and second interconnect level are coupled through a planar slab via. An interconnect line may include a horizontal line segment within one of the first or second interconnect levels, and the slab via may be a vertical line segment between the first and second interconnect levels. A planar slab via may comprise one or more layers of conductive material, which have been deposited upon a planarized substrate material that lacks any features that the conductive material must fill. A planar slab via may be subtractively defined concurrently with a horizontal line of one or both of the first or second interconnect levels.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a device level comprising a plurality of device structures; and
an electrical interconnect structure coupling the device structures into circuitry, wherein the electrical interconnect structure comprises:
a first interconnect line in a first interconnect level, the first interconnect line having a first surface defining a first plane, wherein the first interconnect line extends in a first direction and has a first width;
a second interconnect line in a second interconnect level, the second interconnect line having a second surface defining a second plane, substantially parallel to the first plane, wherein the second line extends in a second direction, non-parallel to the first direction, and has a second width; and
a slab via interconnecting the first interconnect line to the second interconnect line, wherein the slab via has a substantially rectangular cross-section within a plane that is at an interface of the first interconnect line or second interconnect line, and that is substantially parallel to the first plane, wherein a cross-section of the slab via at an interface with the first interconnect line has a first dimension in the second direction that is substantially equal to the first width, or wherein a cross-section of the slab via at an interface of the second interconnect line has a second dimension in the first direction that is substantially equal to the second width.

2. The IC structure of claim 1 , wherein a cross-section of the slab via at the interface with the first interconnect line has a first dimension in the second direction that is substantially equal to the first width, and wherein a cross-section of the slab via at the interface of the second interconnect line has a second dimension in the first direction that is substantially equal to the second width.

3. The IC structure of claim 2 , wherein the cross-section of the slab via at the interface with the first interconnect line has a second dimension in the first direction that is unequal to the second width.

4. The IC structure of claim 3 , wherein the second dimension is greater than the second width.

5. The IC structure of claim 1 , further comprising:
first dielectric material adjacent a first side of the slab via; and
a second dielectric material adjacent to a side of the second interconnect line and a second side of the slab via.

6. The IC structure of claim 1 , wherein a second dimension of the cross-section at the interface of the first interconnect line is substantially equal to the second width, and wherein the first dimension of the cross-section at the interface of the second interconnect line is substantially equal to the first width.

7. The IC structure of claim 1 , wherein the slab via has substantially the same composition as at least one of the first or second interconnect lines.

8. The IC structure of claim 1 , wherein the slab via comprises a stack of two or material layers, and wherein individual layers of the stack are all substantially parallel to the first plane.

9. The IC structure of claim 8 , wherein a first of the material layers interfaces with the first interconnect line and a second of the material layers interfaces with the second interconnect line.

10. The IC structure of claim 1 , wherein the slab via comprises a metal, graphite, or carbon nanotubes.

11. The IC structure of claim 10 , wherein slab via comprises at least one of W, Ru, Mo, Al, or Ti.

12. An integrated circuit (IC) structure, comprising:
a device level comprising semiconductor device structures; and
electrical interconnects coupling the semiconductor device structures into circuitry, wherein the electrical interconnects comprise:
a first interconnect line extending laterally within a first plane; and
a second interconnect line having a first line segment extending laterally within a second plane, and a second line segment extending vertically, substantially orthogonal to the first and second planes, wherein the first and second line segments are compositionally homogeneous, and wherein the second line segment is in contact with the first interconnect line.

13. The IC structure of claim 12 , wherein the second interconnect line has a different composition that the first interconnect line.

14. The IC structure of claim 12 , wherein the first interconnect line is above the second interconnect line.

15. The IC structure of claim 12 , wherein the first interconnect line is below the second interconnect line.

Assignees

• Intel Corp

Inventors

• Karpov Elijah
• Chandhok Manish
• Kabir Nafees

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/093

  by modifying materials of the dielectric parts · CPC title