Fill of vias in single and dual damascene structures using self-assembled monolayer
US-12598977-B2 · Apr 7, 2026 · US
This page is not indexed by search engines while we improve data quality.
Chen Jiun-Ruey patents
Chen Jiun-Ruey is listed as an inventor on 18 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chen Jiun-Ruey |
| Total patents | 18 |
| First publication | May 5, 2022 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Capping layer for transition metal dichalcogenide based transistor structures
US-2026006861-A1 · Jan 1, 2026 · US
Capacitors with amorphous oxide layer for high capacitance and low leakage
US-2025393189-A1 · Dec 25, 2025 · US
Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition
US-12500162-B2 · Dec 16, 2025 · US
Selective conductive cap and liner deposition techniques for interconnects and contact structures
US-2025379149-A1 · Dec 11, 2025 · US
Subtractively patterned interconnect structures for integrated circuits
US-12482744-B2 · Nov 25, 2025 · US
Self-aligned interconnect features with floating dielectric structure
US-2025218868-A1 · Jul 3, 2025 · US
Conformal coatings with spatially defined surface energies for die-to-wafer self-alignment assisted assembly
US-2025112155-A1 · Apr 3, 2025 · US
Subtractively patterned interconnect structures for integrated circuits
US-2024304543-A1 · Sep 12, 2024 · US
Subtractively patterned interconnect structures for integrated circuits
US-12027458-B2 · Jul 2, 2024 · US
Recent patents
Latest publications not already listed above.
Self-assembled monolayer on a dielectric for transition metal dichalcogenide growth for stacked 2d channels
US-2023420510-A1 · Dec 28, 2023 · US
Integrated circuits with max or mx conductive materials
US-2023197836-A1 · Jun 22, 2023 · US
Staggered vertically spaced integrated circuit line metallization with differential vias & metal-selective deposition
US-2023197602-A1 · Jun 22, 2023 · US
Fill of vias in single and dual damascene structures using self-assembled monolayer
US-2023197601-A1 · Jun 22, 2023 · US
Subtractively patterned interconnect structures for integrated circuits
US-2022352068-A1 · Nov 3, 2022 · US
Subtractively patterned interconnect structures for integrated circuits
US-11444024-B2 · Sep 13, 2022 · US
Subtractively patterned interconnect structures for integrated circuits
US-2022139823-A1 · May 5, 2022 · US
Interconnect structures with area selective adhesion or barrier materials for low resistance vias in integrated circuits
US-2022139772-A1 · May 5, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 18 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/42 | 13 |
| H01L23/5226 | 12 |
| H10W20/435 | 10 |
| H10W20/033 | 10 |
| H10W20/47 | 9 |