Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-11990378-B2
Application number	US-202318189437-A
Country	US
Kind code	B2
Filing date	Mar 24, 2023
Priority date	May 27, 2020
Publication date	May 21, 2024
Grant date	May 21, 2024

Abstract

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

First claim

What is claimed is:

1. A method comprising:
depositing a first inter-layer dielectric over an unused region of a first semiconductor fin and over a source/drain region, the source/drain region formed in a second semiconductor fin;
forming a cut mask over the first inter-layer dielectric, the cut mask comprising a trim portion, the trim portion overlapping the unused region in a top-down view;
forming a line mask over the cut mask, the line mask comprising a slot opening, the slot opening overlapping the unused region and the source/drain region in the top-down view;
extending the slot opening through a portion of the first inter-layer dielectric uncovered by the line mask and the cut mask to form a contact opening exposing the source/drain region; and
forming a first contact in the contact opening, the first contact contacting the source/drain region.

2. The method of claim 1 , further comprising:
forming a first gate spacer and a second gate spacer, the source/drain region disposed between the first gate spacer and the second gate spacer, the unused region disposed between the first gate spacer and the second gate spacer.

3. The method of claim 1 , further comprising:
forming a gate structure over the first semiconductor fin and the second semiconductor fin.

4. The method of claim 3 , further comprising:
depositing a second inter-layer dielectric over the first inter-layer dielectric and over the gate structure; and
forming a second contact in the second inter-layer dielectric, the second contact contacting the first contact.

5. The method of claim 1 , wherein a width of the slot opening is less than a width of the trim portion.

6. The method of claim 1 , wherein the cut mask further comprises a first cut portion and a second cut portion, the trim portion connecting the first cut portion to the second cut portion, the first semiconductor fin disposed between the first cut portion and the second cut portion in the top-down view.

7. A method comprising:
depositing a dielectric layer over a first dummy region of a semiconductor fin;
forming a cut mask over the dielectric layer, the cut mask comprising a first cut portion, a second cut portion, and a first trim portion, the first trim portion connecting the first cut portion to the second cut portion, the first trim portion overlapping the first dummy region;
forming a line mask over the cut mask, the line mask comprising a first slot opening, the first slot opening overlapping the first trim portion; and
patterning the dielectric layer using the line mask and the cut mask as a combined etching mask.

8. The method of claim 7 , wherein the cut mask further comprises a second trim portion, the second trim portion connecting the first cut portion to the second cut portion, the second trim portion overlapping a second dummy region of the semiconductor fin, and the line mask further comprises a second slot opening, the second slot opening overlapping the second trim portion.

9. The method of claim 8 , wherein the first cut portion is separated from the second cut portion by a first distance, the first trim portion is separated from the second trim portion by a second distance, and the second distance is greater than the first distance.

10. The method of claim 8 , wherein the first cut portion is separated from the second cut portion by a first distance, the first trim portion is separated from the second trim portion by a second distance, and the second distance is less than the first distance.

11. The method of claim 8 , further comprising:
forming a source/drain region in the semiconductor fin, the source/drain region disposed between the first dummy region and the second dummy region.

12. The method of claim 8 , further comprising:
forming a gate structure over the semiconductor fin, the gate structure disposed between the first dummy region and the second dummy region.

13. The method of claim 7 , wherein the dielectric layer is a masking layer.

14. The method of claim 7 , wherein the dielectric layer is an etch stop layer.

15. A method comprising:
depositing a dielectric layer over a dummy region of a first semiconductor fin and over a source/drain region, the source/drain region formed in a second semiconductor fin, the first semiconductor fin being adjacent to the second semiconductor fin in a first direction;
forming a cut mask over the dielectric layer, the cut mask comprising a trim portion, the trim portion covering a first portion of the dielectric layer over the dummy region;
forming a line mask over the cut mask, the line mask comprising a slot opening, the slot opening exposing the trim portion and a second portion of the dielectric layer over the source/drain region, the slot opening extending continuously from over the trim portion to over the second portion of the dielectric layer along the first direction; and
removing the second portion of the dielectric layer to form a contact opening over the source/drain region, the first portion of the dielectric layer remaining over the dummy region.

16. The method of claim 15 , further comprising:
forming a contact in the contact opening, the contact contacting the source/drain region.

17. The method of claim 15 , further comprising:
after removing the second portion of the dielectric layer, removing the first portion of the dielectric layer.

18. The method of claim 15 , further comprising:
forming a gate spacer adjacent the dummy region and the source/drain region.

19. The method of claim 15 , wherein removing the second portion of the dielectric layer comprises etching the dielectric layer using the line mask as an etching mask and using the cut mask as an etch stop layer.

20. The method of claim 15 , wherein the dielectric layer is a masking layer formed over an inter-layer dielectric, the method further comprising:
patterning the inter-layer dielectric using the masking layer as an etching mask.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien-Yuan
• Lin Jui-Ping
• Lee Chen-Ming
• Yang Fu-Kai
• Wang Mei-Yun

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P50/667

  by liquid etching only · CPC title