Self-aligned scheme for semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-11901228-B2
Application number	US-202117371416-A
Country	US
Kind code	B2
Filing date	Jul 9, 2021
Priority date	Mar 31, 2021
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.

First claim

What is claimed is:

1. A method comprising:
forming a first conductive feature in a first inter-metal dielectric (IMD) layer, the first conductive feature comprising a capping layer;
selectively depositing a blocking film over and physically contacting the first conductive feature, a material of the blocking film comprising a hydrophilic group and a hydrophobic group;
depositing a first dielectric layer over and physically contacting the first IMD layer;
depositing a second dielectric layer over and physically contacting the first dielectric layer;
removing the blocking film;
depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer;
forming a second IMD layer over the etch stop layer;
etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and
forming a second conductive feature in the opening.

2. The method of claim 1 , wherein the first dielectric layer is a low-k dielectric material, and wherein the second dielectric layer is a high-k dielectric material.

3. The method of claim 1 , wherein the etch stop layer and the second dielectric layer comprise different etch selectivities.

4. The method of claim 1 , wherein removing the blocking film comprises selectively removing the blocking film.

5. The method of claim 1 , wherein etching the opening further exposes a portion of the second dielectric layer.

6. The method of claim 5 , wherein during the etching the opening, an entirety of the first IMD layer directly below the portion of the second dielectric layer remains unetched.

7. The method of claim 5 , wherein during the etching the opening, the first dielectric layer is etched by a greater amount than the second dielectric layer.

8. The method of claim 1 , wherein forming the first conductive feature in the first IMD layer comprises:
etching an additional opening in the first IMD layer;
depositing a liner layer in the opening;
depositing a conductive fill material over the liner layer; and
depositing the capping layer over the conductive fill material.

9. A method comprising:
forming a first conductive feature and a second conductive feature in a first dielectric layer, an exposed surface of the first conductive feature comprising a first capping layer, an exposed surface of the second conductive feature comprising a second capping layer;
forming a blocking layer over the first conductive feature and the second conductive feature, the blocking layer having a greater deposition selectivity over the first conductive feature and the second conductive feature than over the first dielectric layer, the blocking layer comprising hydrophilic groups and hydrophobic groups;
forming a multilayer dielectric over the first dielectric layer and laterally displaced from the blocking layer, the multilayer dielectric comprising a low-k dielectric layer disposed over the first dielectric layer and a high-k dielectric layer disposed over the low-k dielectric layer;
flowing a reacting gas to remove the blocking layer;
depositing an etch stop layer over the high-k dielectric layer;
depositing a second dielectric layer over the etch stop layer;
forming a trench in the second dielectric layer and the etch stop layer, the forming the trench comprising exposing the first conductive feature and the high-k dielectric layer; and
forming a third conductive feature in the trench.

10. The method of claim 9 , wherein the forming the trench comprises etching portions of the second dielectric layer, the etch stop layer, and the low-k dielectric layer.

11. The method of claim 10 , wherein the etch stop layer and the high-k dielectric layer have a high etch selectivity.

12. The method of claim 9 , wherein the third conductive feature comprises a bulk portion extending to a top surface of the first conductive feature and an overbite portion extending to a top surface of the high-k dielectric layer.

13. The method of claim 12 , wherein the first conductive feature is a first distance from the second conductive feature, wherein the third conductive feature is a second distance from the second conductive feature, and wherein the second distance is less than the first distance.

14. The method of claim 9 , wherein the reacting gas comprises H 2 and/or NH 3 .

15. The method of claim 9 , wherein the low-k dielectric layer comprises silicon oxide, and wherein the high-k dielectric layer comprises aluminum oxide.

16. A method comprising:
forming a first conductive feature in a first dielectric layer, a top surface of the first conductive feature being above a top surface of the first dielectric layer, forming the first conductive feature comprising:
forming a conductive material in the first dielectric layer; and
forming a capping layer over the conductive material;

depositing a blocking layer along the top surface of the first conductive feature, a molecule of the blocking layer comprising a hydrophilic head group and a hydrophobic tail group;
depositing a low-k dielectric layer along the top surface of the first dielectric layer, a top surface of the low-k dielectric layer being above the top surface of the first conductive feature;
depositing a high-k dielectric layer over the low-k dielectric layer;
removing the blocking layer;
forming a second dielectric layer over the high-k dielectric layer;
etching an opening in the second dielectric layer to expose the first conductive feature; and
forming a second conductive feature in the opening.

17. The method of claim 16 , wherein etching the opening in the second dielectric layer comprises exposing a sidewall of the low-k dielectric layer.

18. The method of claim 17 , wherein etching the opening in the second dielectric layer comprises etching a portion of the low-k dielectric layer, and wherein a portion of the opening is directly below the high-k dielectric layer.

19. The method of claim 18 , wherein forming the second conductive feature comprises depositing a liner layer in the portion of the opening.

20. The method of claim 16 , wherein the blocking layer comprises a self-assembling monolayer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu cai-ling
• Hsueh Hsiu-Wen
• Wang Wei-Ren
• Huang Po-Hsiang
• Chen Chii-Ping
• Wang Jen Hung

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title