Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11784256-B2
Application number	US-202117556001-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Dec 8, 2017
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A semiconductor device may include first and second channel patterns on a substrate, first and second source/drain patterns in contact respectively with the first and second channel patterns, and first and second gate electrodes respectively overlapping the first and second channel patterns. The first gate electrode may include a first segment between first and second semiconductor patterns of the first channel pattern. The first segment may include a first convex portion protruding toward the first source/drain pattern. The second gate electrode may include a second segment between third and fourth semiconductor patterns of the second channel pattern. The second segment may include a concave portion recessed toward a center of the second segment.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region that are adjacent to each other;
a first channel pattern on the PMOSFET region, the first channel pattern including a plurality of first semiconductor patterns that are sequentially stacked on the PMOSFET region and vertically spaced apart from each other;
a second channel pattern on the NMOSFET region, the second channel pattern including a plurality of second semiconductor patterns that are sequentially stacked on the NMOSFET region and vertically spaced apart from each other;
a first source/drain pattern on the PMOSFET region, the first source/drain pattern being connected to the plurality of first semiconductor patterns;
a second source/drain pattern on the NMOSFET region, the second source/drain pattern being connected to the plurality of second semiconductor patterns;
a gate electrode on the first and second channel patterns, the gate electrode extending from the PMOSFET region to the NMOSFET region, the gate electrode including a first segment between adjacent ones of the plurality of first semiconductor patterns and a second segment between adjacent ones of the plurality of second semiconductor patterns; and
a barrier insulation pattern between the second segment of the gate electrode and the second source/drain pattern,
wherein the barrier insulation pattern includes a silicon nitride layer,
wherein a barrier insulating pattern is omitted between the first segment of the gate electrode and the first source/drain pattern, and
wherein a sidewall of the first segment has a convex profile corresponding to a side recession of the first source/drain pattern.

2. The semiconductor device of claim 1 , wherein a sidewall of the second segment has a concave profile corresponding to the barrier insulation pattern.

3. The semiconductor device of claim 1 , further comprising:
a first gate dielectric pattern between the first segment and the adjacent ones of the plurality of first semiconductor patterns; and
a second gate dielectric pattern between the second segment and the adjacent ones of the plurality of second semiconductor patterns,
wherein the first gate dielectric pattern directly contacts the first source/drain pattern.

4. The semiconductor device of claim 3 , wherein the second gate dielectric pattern directly contacts the barrier insulating pattern.

5. The semiconductor device of claim 1 , further comprising:
a pair of gate spacers on opposite sidewalls of the gate electrode, respectively; and
a gate capping pattern on a top surface of the gate electrode.

6. The semiconductor device of claim 1 , wherein a width of the first segment is greater than a width of the second segment.

7. The semiconductor device of claim 1 , wherein a curvature of a bottom surface of the first source/drain pattern is greater than a curvature of a bottom surface of the second source/drain pattern.

8. The semiconductor device of claim 1 , wherein the barrier insulation pattern has a convex portion protruding toward the second segment of the gate electrode.

9. The semiconductor device of claim 1 , wherein a maximum width of the first source/drain pattern is greater than a maximum width of the second source/drain pattern.

10. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region that are adjacent to each other;
a first channel pattern on the PMOSFET region, the first channel pattern including a plurality of first semiconductor patterns that are sequentially stacked on the PMOSFET region and vertically spaced apart from each other;
a second channel pattern on the NMOSFET region, the second channel pattern including a plurality of second semiconductor patterns that are sequentially stacked on the NMOSFET region and vertically spaced apart from each other;
a first source/drain pattern on the PMOSFET region, the first source/drain pattern being connected to the plurality of first semiconductor patterns;
a second source/drain pattern on the NMOSFET region, the second source/drain pattern being connected to the plurality of second semiconductor patterns;
a gate electrode on the first and second channel patterns, the gate electrode extending from the PMOSFET region to the NMOSFET region, the gate electrode including a first segment between adjacent ones of the plurality of first semiconductor patterns and a second segment between adjacent ones of the plurality of second semiconductor patterns; and
a barrier insulation pattern between the second segment of the gate electrode and the second source/drain pattern,
wherein a curvature of a bottom surface of the first source/drain pattern is greater than a curvature of a bottom surface of the second source/drain pattern, and
wherein a sidewall of the first segment has a convex profile corresponding to a side recession of the first source/drain pattern.

11. The semiconductor device of claim 10 , wherein a sidewall of the second segment has a concave profile corresponding to the barrier insulation pattern.

12. The semiconductor device of claim 10 , further comprising:
a first gate dielectric pattern between the first segment and the adjacent ones of the plurality of first semiconductor patterns; and
a second gate dielectric pattern between the second segment and the adjacent ones of the plurality of second semiconductor patterns,
wherein the first gate dielectric pattern directly contacts the first source/drain pattern, and
wherein the second gate dielectric pattern directly contacts the barrier insulating pattern.

13. The semiconductor device of claim 10 , wherein the barrier insulation pattern has a convex portion protruding toward the second segment of the gate electrode.

14. A semiconductor device, comprising:
a substrate including a PMOSFET region and an NMOSFET region that are adjacent to each other;
a first channel pattern on the PMOSFET region, the first channel pattern including first, second and third semiconductor patterns that are sequentially stacked on the PMOSFET region and vertically spaced apart from each other;
a second channel pattern on the NMOSFET region, the second channel pattern including fourth, fifth and sixth semiconductor patterns that are sequentially stacked on the NMOSFET region and vertically spaced apart from each other;
a first source/drain pattern on the PMOSFET region, the first source/drain pattern being connected to the first semiconductor patterns;
a second source/drain pattern on the NMOSFET region, the second source/drain pattern being connected to the second semiconductor patterns; and
a gate electrode on the first and second channel patterns, the gate electrode extending from the PMOSFET region to the NMOSFET region,
wherein the gate electrode includes:
a first segment between the substrate and the first semiconductor pattern, a second segment between the first semiconductor pattern and the second semiconductor pattern, and a third segment between the second semiconductor pattern and the third semiconductor pattern; and
a fourth segment between the substrate and the fourth semiconductor pattern, a fifth segment between the fourth semiconductor pattern and the fifth semiconductor pattern, and a sixth segment between the fifth semiconductor pattern and the sixth semiconductor pattern,

wherein a width of the first segment is greater than a width of the second segment, and greater than a width of the third segment,
wherein a width of the fourth segment is greater than a width of the fifth segment,
wherein the width of the fifth segment is greater than a width of the sixth se

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Soojin
• Bae Dong Il
• Bae Geumjong
• Song Seungmin
• Yang Junggil

Classifications

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title