Multi-channel gate-all-around FET

Patent metadata

Field	Value
Publication number	US-9502518-B2
Application number	US-201414312418-A
Country	US
Kind code	B2
Filing date	Jun 23, 2014
Priority date	Jun 23, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wrap-around gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

First claim

The invention claimed is:

1. A transistor, comprising:
a source region;
a drain region;
a stacked array of nanowires electrically coupling the doped source and drain regions, the stacked array including rows and columns of nanowires, each nanowire having end portions and a central portion;
a gate stack fully surrounding the central portions of the nanowires and filling a volume of space between the nanowires;
a hard mask in contact with an upper surface of one or more of the end portions of a first one of the nanowires, the hard mask having a hard mask width sufficient to form an electrically insulating barrier between the gate stack and the source and drain regions, wherein the gate stack includes a conductive gate and a gate dielectric that contacts the central portion of the first nanowire and separates the conductive gate from the first nanowire, the gate dielectric being of a different material than the hard mask, and the hard mask being positioned between the gate dielectric and at least one of the source and drain regions.

2. The transistor of claim 1 wherein the transistor is a PFET and the source and drain regions are made of boron-doped SiGe.

3. The transistor of claim 1 wherein the transistor is an NFET and the source and drain regions are made of one of silicon or silicon carbide, doped with one of arsenic or phosphorous.

4. The transistor of claim 1 wherein the nanowires have substantially circular cross-sections.

5. The transistor of claim 1 further comprising first and second insulators that electrically isolate the conductive gate from the source and drain regions, respectively, the first insulator contacting an opposite side of the first nanowire with respect to the hard mask.

6. The transistor of claim 5 wherein the first and second insulators have widths that are less than a width of the hard mask.

7. The transistor of claim 1 wherein the conductive gate is a metal gate and the gate dielectric is a high-k gate dielectric that separates the metal gate from the first nanowire.

8. A gate-all-around transistor, comprising:
a doped source region;
a doped drain region;
a vertically stacked array of nanowires coupling the source and drain regions, the vertically stacked array including rows and columns of nanowires;
a hard mask remaining in contact with an upper surface of one or more of the nanowires;
a conductive gate that fully surrounds central portions of the nanowires;
first and second insulators that electrically isolate the metal gate from the source and drain regions; and
sidewall spacers covering sidewalls of the conductive gate, the sidewall spacers overlying and aligned with the hard mask.

9. The transistor of claim 8 wherein a channel length between the source and drain regions is less than about 20 nm.

10. The transistor of claim 8 wherein the array of nanowires carries a linear drain current density within the range of about 0.5-3.0 mA/μm.

11. The transistor of claim 8 wherein the sidewall spacers have a sidewall spacer width that is substantially equal to the hard mask width.

12. A transistor, comprising:
a source region;
a drain region;
a stacked array of nanowires electrically coupling the doped source and drain regions, the stacked array including rows and columns of nanowires, each nanowire having end portions and a central portion;
a gate stack fully surrounding the central portions of the nanowires and filling a volume of space between the nanowires;
a hard mask in contact with an upper surface of one or more of the end portions, the hard mask having a hard mask width sufficient to form an electrically insulating barrier between the gate stack and the source and drain regions; and
first and second insulators that electrically isolate the gate stack from the source and drain regions, wherein the gate stack has a first gate width above the nanowires, the first gate width determined by a width of the hard mask, and a second gate width below the nanowires, the second gate width determined by widths of the first and second insulators.

13. The transistor of claim 12 wherein the first gate width is narrower than the second gate width.

14. The transistor of claim 12 , wherein the transistor is a PFET and the source and drain regions are made of boron-doped SiGe.

15. The transistor of claim 12 , wherein the transistor is an NFET and the source and drain regions are made of one of silicon or silicon carbide, doped with one of arsenic or phosphorous.

16. The transistor of claim 12 , wherein the nanowires have substantially circular cross-sections.

17. The transistor of claim 12 , wherein the hard mask contacts a first side of an end of a first one of the nanowires and the first insulator contacts a second side of the end of the first nanowire, the first side being opposite to the second side.

18. The transistor of claim 12 , wherein the gate stack includes a metal gate and a high-k gate dielectric that separates the metal gate from at least one of the nanowires.

Assignees

• St Microelectronics Inc
• Globalfoundries Inc
• IBM

Inventors

• Liu Qing
• Xie Ruilong
• Yeh Chun-Chen
• Cai Xiuyu

Classifications

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/8325

  Silicon carbide · CPC title