Semiconductor device having a gate all around structure

Patent metadata

Field	Value
Publication number	US-9601569-B1
Application number	US-201514961378-A
Country	US
Kind code	B1
Filing date	Dec 7, 2015
Priority date	Dec 7, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A semiconductor includes a substrate including a first region and a second region, a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other, a first wire pattern extending in a second direction in the second region of the substrate, a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction, and a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a first region and a second region;
a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other;
a first wire pattern extending in a second direction in the second region of the substrate;
a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction; and
a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.

2. The semiconductor device of claim 1 , wherein the first semiconductor pattern is disposed at a first height with respect to an upper surface of the substrate, the second semiconductor pattern is disposed at a second height with respect to the upper surface of the substrate, the second height is different from the first height, and the first wire pattern is disposed at the first height and includes the same material as the first semiconductor pattern.

3. The semiconductor device of claim 2 , wherein a thickness of the first semiconductor pattern is equal to a thickness of the first wire pattern.

4. The semiconductor device of claim 3 , wherein a width in which the first gate electrode and the fin overlap each other is different from a width in which the second gate electrode and the first wire pattern overlap each other.

5. The semiconductor device of claim 4 , wherein the width in which the first gate electrode and the fin overlap each other is larger than the width in which the second gate electrode and the first wire pattern overlap each other.

6. The semiconductor device of claim 1 , further comprising a first source or drain arranged on first and second sides of the first gate electrode, and a second source or drain arranged on first and second sides of the second gate electrode,
wherein the first source or drain includes an extension portion of the first semiconductor pattern and an extension portion of the second semiconductor pattern, and the second source or drain includes a third semiconductor pattern and a fourth semiconductor pattern that are disposed on each other.

7. The semiconductor device of claim 1 , wherein the substrate further includes a third region, and the semiconductor device further comprises a second wire pattern extending in a fifth direction on the third region and a third gate electrode surrounding an outer perimeter of the second wire pattern and extending in a sixth direction that is different from the fifth direction.

8. The semiconductor device of claim 7 , wherein the first semiconductor pattern is disposed at a first height with respect to an upper surface of the substrate, the second semiconductor pattern is disposed at a second height with respect to the upper surface of the substrate, the second height is different from the first height, the first wire pattern is disposed at the first height and includes the same material as the first semiconductor pattern, and the second wire pattern is disposed at the second height and includes the same material as the second semiconductor pattern.

9. The semiconductor device of claim 8 , wherein the first wire pattern and the second wire pattern include different materials.

10. The semiconductor device of claim 7 , wherein a thickness of the first semiconductor pattern is equal to a thickness of the first wire pattern, and a thickness of the second semiconductor pattern is equal to a thickness of the second wire pattern.

11. The semiconductor device of claim 7 , wherein a width in which the first gate electrode and the fin overlap each other is different from a width in which the second gate electrode and the first wire pattern overlap each other, and wherein the width in which the first gate electrode and the fin overlap each other is different from a width in which the third gate electrode and the second wire pattern overlap each other.

12. A semiconductor device comprising:
a substrate including a first region and a second region;
a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern;
a wire pattern extending in a second direction in the second region of the substrate;
a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction; and
a second gate electrode surrounding an outer perimeter of the wire pattern and extending in a fourth direction that is different from the second direction,
wherein a width of the second gate electrode is different from a width of the first gate electrode.

13. The semiconductor device of claim 12 , wherein the width of the first gate electrode is larger than the width of the second gate electrode.

14. The semiconductor device of claim 12 , wherein the first semiconductor pattern is disposed at a first height with respect to an upper surface of the substrate, the second semiconductor pattern is disposed at a second height with respect to the upper surface of the substrate, the second height is different from the first height, and the first wire pattern is disposed at the first height and includes the same material as the first semiconductor pattern.

15. The semiconductor device of claim 14 , wherein a thickness of the first semiconductor pattern is equal to a thickness of the first wire pattern.

16. A semiconductor device comprising:
a substrate including a first region and a second region;
a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern disposed on the substrate, a second semiconductor pattern disposed on the first semiconductor pattern, a third semiconductor pattern disposed on the second semiconductor pattern, a fourth semiconductor pattern disposed on the third semiconductor pattern, and a fifth semiconductor pattern disposed on the fourth semiconductor pattern;
a first wire pattern extending in a second direction in the second region of the substrate;
a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction; and
a second gate electrode surrounding a circumference of the first wire pattern and extending in a fourth direction that is different from the second direction.

17. The semiconductor device of claim 16 , wherein the third semiconductor pattern is disposed at a first height with respect to an upper surface of the substrate, the fourth semiconductor pattern is disposed at a second height with respect to the upper surface of the substrate, the second height is different from the first height, and the first wire pattern is disposed at the first height and includes the same material as the third semiconductor pattern.

18. The semiconductor device of claim 16 , wherein a width of an area where the first gate electrode and the fin overlap each other is different from a width of an area where the second gate electrode and the first wire pattern overlap each other.

19. The semiconductor device of claim 16 , further comprising a first source or drain arranged on first and second sides of the first gate electrode, and a second source or drain arranged on first and second sides of the second gate electrode,
wherein the first source or drain include

Assignees

• Samsung Electronics Co Ltd

Inventors

• Suk Sung-Dae
• Seo Kang-Ill

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L27/1211

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/0673 Primary

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic