Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9614068-B2
Application number	US-201514843231-A
Country	US
Kind code	B2
Filing date	Sep 2, 2015
Priority date	Sep 2, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first active region;
a field insulating layer disposed in the first active region;
a first nanowire pattern disposed on the first active region and extended in a first direction, wherein the first nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction;
a first gate disposed on the first active region and extended in a second direction crossing the first direction, wherein the first gate entirely covers the first part of the first nanowire pattern; and
a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern,
wherein the first gate comprises a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

2. The semiconductor device of claim 1 , further comprising:
a second nanowire pattern disposed on the first nanowire pattern and extended in the first direction,
wherein the second region of the first gate is disposed between the first nanowire pattern and the first active region.

3. The semiconductor device of claim 2 , further comprising:
a source or drain impurity layer disposed in the first active region, wherein the source or drain impurity layer is not overlapped with the second region of the first gate.

4. The semiconductor device of claim 1 , further comprising:
a first dummy gate overlapped with the field insulating layer and the first active region and spaced apart from the first gate in the first direction,
wherein a width of a region in which the first active region and the first dummy gate are overlapped with each other is wider than a width of a region in which the second part of the first nanowire pattern and the first dummy gate are overlapped with each other.

5. The semiconductor device of claim 1 , further comprising:
a second active region spaced apart from the first active region;
a second nanowire pattern disposed on the second active region and extended in the first direction, wherein the second nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction; and
a second gate disposed on the second active region and extended in the second direction, wherein the second gate entirely covers the first part of the second nanowire pattern,
wherein the second gate comprises a third region disposed on the first part of the second nanowire pattern and having the first width, and a fourth region disposed beneath the first part of the second nanowire pattern and having a third width wider than the first width and different from the second width.

6. The semiconductor device of claim 5 , further comprising:
a third nanowire pattern disposed on the second nanowire pattern and extended in the first direction,
wherein the fourth region of the second gate is disposed between the second nanowire pattern and the second active region.

7. The semiconductor device of claim 1 , further comprising:
a second active region spaced apart from the first active region;
a second nanowire pattern disposed on the second active region and extended in the first direction, wherein the second nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction; and
a second gate disposed on the second active region and extended in the second direction, wherein the second gate entirely covers the first part of the second nanowire pattern and is disposed on the first part of the second nanowire pattern and beneath the first part of the second nanowire pattern,
wherein a width of the second gate disposed on the first part of the second nanowire pattern and a width of the second gate disposed beneath the first part of the second nanowire pattern are substantially the same as each other.

8. A semiconductor device, comprising:
a first active region;
a field insulating layer disposed in the first active region;
a first nanowire pattern disposed on the first active region and extended in a first direction, wherein the first nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction;
a first gate disposed on the first active region and extended in a second direction crossing the first direction, wherein the first gate entirely covers the first part of the first nanowire pattern;
a first source or drain impurity layer disposed in the first active region; and
a first source or drain epitaxial layer disposed on at least one side of the first part of the first nanowire pattern,
wherein the first source or drain epitaxial layer comprises an upper region having a first width and a lower region having a second width narrower than the first width.

9. The semiconductor device of claim 8 , wherein the first source or drain epitaxial layer contacts the first source or drain impurity layer.

10. The semiconductor device of claim 8 , wherein a width of a region in which the first active region and the first gate are overlapped with each other is wider than a width of a region in which the first part of the first nanowire pattern and the first gate are overlapped with each other.

11. The semiconductor device of claim 10 , further comprising:
a first dummy gate overlapped with the field insulating layer and the first active region and spaced apart from the first gate in the first direction,
wherein a width of a region in which the first active region and the first dummy gate are overlapped with each other is wider than a width of a region in which the second art of the first nanowire pattern and the first dummy gate are overlapped with each other.

12. The semiconductor device of claim 8 , further comprising:
a second active region spaced apart from the first active region;
a second nanowire pattern disposed on the second active region and extended in the first direction, wherein the second nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction;
a second gate disposed on the second active region and extended in the second direction, wherein the second gate entirely covers the first part of the second nanowire pattern; and
a plurality of second source or drain impurity layers disposed in the second active region,
wherein the first source or drain impurity layer is one of a plurality of first source or drain impurity layers disposed in the first active region, and a distance between the first source or drain impurity layers is different from a distance between the second source or drain impurity layers.

13. The semiconductor device of claim 8 , further comprising:
a second active region spaced apart from the first active region;
a second nanowire pattern disposed on the second active region and extended in the first direction, wherein the second nanowire pattern comprises a first part, a second part, and a third part spaced apart from one another in the first direction;
a second gate disposed on the second active region and extended in the second direction, wherein the second gate entirely covers the first part of the second nanowire pattern;
a second source or drain impurity layer disposed in the second active region; and
a second source or drain epitaxial layer disposed on at least one side of the first part of the second nanowire pattern,
wherein the second source or drain epitaxial layer comprises a lower region having a third width narrower than the first width and different from the s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Kang-Ill

Classifications

• H01L29/42392

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic

• H01L29/775 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H10D62/121

  oriented parallel to substrates · CPC title