Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9362397-B2
Application number	US-201414464785-A
Country	US
Kind code	B2
Filing date	Aug 21, 2014
Priority date	Sep 24, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor pattern and a second semiconductor pattern sequentially stacked on one another on a substrate;
a gate electrode on the second semiconductor pattern extending into a gap region delimited by a sidewall of the first semiconductor pattern and a bottom surface of the second semiconductor pattern;
a gate insulating layer between the gate electrode and the first and second semiconductor patterns;
a semiconductor oxide between the gate insulating layer and the first semiconductor pattern, the semiconductor oxide having a dielectric constant that is less than that of the gate insulating layer,
wherein the semiconductor oxide extends between the gate electrode and the substrate,
a source region on a first side of the gate electrode; and
a drain region on a second side of the gate electrode opposite the first side, wherein the semiconductor oxide and the gate insulating layer are located together on both the first and second sides of the gate electrode located between tops and bottoms of the source and drain regions so that the semiconductor oxide and the gate insulating layer are configured to reduce parasitic coupling between the gate electrode and the first semiconductor pattern.

2. The device of claim 1 , wherein the first semiconductor pattern comprises a material having an etch selectivity with respect to the second semiconductor pattern and has an oxidation rate that is greater than that of the second semiconductor pattern.

3. The device of claim 1 , wherein the first and second semiconductor patterns each comprise a respective epitaxial layer.

4. The device of claim 1 , further comprising:
wherein the source and drain regions penetrate the first and second semiconductor patterns respectively; and
wherein each of the source and drain regions comprise at least one of single crystalline semiconductor materials, conductive metal nitrides, and metals.

5. The device of claim 1 , wherein the first semiconductor pattern comprises a portion between the semiconductor oxide and the substrate.

6. The device of claim 1 , wherein the gate electrode has a metal gate structure including at least one of a conductive metal nitride layer and a metal layer.

7. The device of claim 1 , further comprising:
a third semiconductor pattern on the second semiconductor pattern; and
a fourth semiconductor pattern on the third semiconductor pattern, the fourth semiconductor pattern penetrating the gate electrode,
wherein the third and first semiconductor patterns comprise a first material, and the fourth and second semiconductor patterns comprise a second material.

8. The device of claim 7 , wherein the first semiconductor pattern is thicker than the third semiconductor pattern.

9. A gate-all-around (GAA) semiconductor device, comprising:
a fin structure including alternatingly layered first and second semiconductor patterns;
a source region extending into the alternatingly layered first and second semiconductor patterns;
a drain region extending into the alternatingly layered first and second semiconductor patterns;
a gate electrode extending between the source region and the drain region and surrounding channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions;
a semiconductor oxide on first side walls of the gaps that face the source and drain regions and absent from at least one of second side walls of the gaps that face the second semiconductor patterns; and
a gate insulating layer on the first side walls of the gaps between the gate electrode and the semiconductor oxide, wherein the first semiconductor patterns are on the first side walls of the gaps on the gate insulating layer opposite the semiconductor oxide, wherein the semiconductor oxide has a dielectric constant that is less than that of the gate insulating layer such that the semiconductor oxide and the gate insulating layer are configured to reduce parasitic coupling between the gate electrode and the first semiconductor pattern.

10. The GAA device of claim 9 wherein the semiconductor oxide is located on lowest one of the second side walls between the gate electrode and the substrate.

11. The GAA device of claim 9 wherein the gate insulating layer surrounds the channel portions.

12. The GAA device of claim 11 wherein the gate insulating layer contacts the channel portions.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hur Sung Gi
• Kim Sangsu
• Yang Junggil
• Yang Changjae
• Lee Dongkyu

Classifications

• H10D62/81

  of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/026

  having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289) · CPC title

• H10D30/023

  having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title