Forming a hybrid channel nanosheet semiconductor structure

Patent metadata

Field	Value
Publication number	US-9704863-B1
Application number	US-201615260509-A
Country	US
Kind code	B1
Filing date	Sep 9, 2016
Priority date	Sep 9, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.

First claim

What is claimed is:

1. A method for fabricating a nanosheet semiconductor structure, the method comprising:
forming a first nanosheet field effect transistor (FET) structure having a first inner spacer comprised of a first material and a second nanosheet FET structure having a second inner spacer comprised of a second material;
wherein the first material is different than the second material; and
wherein forming the first nanosheet FET structure and the second nanosheet FET structure comprises:
creating a first inner spacer formation within a first silicon germanium (SiGe) channel comprised in a first channel region of a first FET region and a second inner spacer formation within a second SiGe channel comprised in a second channel region of a second FET region, wherein the first SiGe channel is formed from one or more first SiGe nanosheets and the second SiGe channel is formed from one or more second SiGe nanosheets;
depositing a first sacrificial liner on the first FET region and a second sacrificial liner on the second FET region;
forming a mask on the second sacrificial liner;
forming a first source/drain region along a first silicon (Si) channel of the first channel region, wherein the first Si channel is formed from one or more first Si nanosheets;
removing the mask and the first and second sacrificial liners;
creating a third inner spacer formation within a second Si channel comprised in the second channel region, wherein the second Si channel is formed from one or more second Si nanosheets;
forming a second source/drain region along the second SiGe channel;
filling the first source/drain region with a first oxide and the second source/drain region with a second oxide;
replacing a first gate of the first FET region with a first metal and the first SiGe channel with a first work function metal; and
replacing a second gate of the second FET region with a second metal and the second Si channel with a second work function metal.

2. The method of claim 1 , where in the first nanosheet FET structure is an n-type FET structure and the second nanosheet FET structure is a p-type FET structure.

3. The method of claim 1 , wherein the first channel region is formed via etching.

4. The method of claim 1 , further comprising:
forming a first stack on the first FET region and a second stack on the second FET region, wherein the first stack comprises a first substrate, the one or more first Si nanosheets, and the one or more first SiGe nanosheets, and wherein the second stack comprises the second substrate, the one or more second Si nanosheets, and the one or more second SiGe nanosheets;
forming a first pad insulator on the first channel region and a second pad insulator on the second channel region;
forming a first gate on the first pad insulator and a second gate on the second pad insulator;
forming a first hard mask on the first gate and a second hard mask on the second gate;
forming a first spacer on the first channel region, the first gate, and the first hard mask, and a second spacer on the second channel region, the second gate, and the second hard mask, wherein each spacer comprises silicon mononitride (SiN); and
forming the first channel region from the first stack and the second channel region from the second stack.

5. The method of claim 4 , wherein the first substrate is comprised of Si.

6. The method of claim 1 , wherein creating the first inner spacer formation comprises forming a first divot within the first SiGe channel and filling the first divot with a first ceramic material, and wherein creating the second inner spacer formation comprises forming a second divot within the second SiGe channel and filling the second divot with a second ceramic material.

7. The method of claim 6 , wherein the first ceramic material is comprised of silicon-boron-carbide-nitride (SiBCN).

8. The method of claim 6 , wherein the first divot is formed via etching.

9. The method of claim 1 , wherein creating the third inner spacer region comprises forming a divot within the second Si channel and filling the divot with a silicate glass.

10. The method of claim 9 , wherein the silicate glass is silicon oxycarbide (SiCO).

11. The method of claim 1 , wherein the first and second source/drain regions are formed via an epitaxial growth process.

12. The method of claim 1 , wherein the first and second gates are comprised of polysilicon, and wherein replacing the first and second gates comprises removing the first and second gates via a polysilicon pull process.

13. The method of claim 1 , wherein replacing the first Si channel comprises performing a Si channel release, and wherein replacing the second SiGe channel comprises performing a SiGe channel release.

14. The method of claim 1 , wherein the first metal is comprised of tungsten (W).

15. The method of claim 1 , further comprising performing a first chemical mechanical planarization (CMP) process after replacing the first gate and the first Si channel, and a second CMP process after replacing the second gate and the second SiGe channel.

16. The method of claim 1 , wherein at least one of the first work function metal and the second work function metal is deposited via a conformal atomic layer deposition (ALD) process.

17. The method of claim 1 , wherein at least one of the first metal and the second is deposited via a plasma-enhanced chemical vapor deposition (PECVD) process.

18. The method of claim 15 , further comprising forming a first gate cap layer on the first FET region and a second gate cap layer on the second FET region.

19. The method of claim 18 , wherein forming the first gate cap layer and the second gate cap layer comprises etching the first metal and the second metal to form recesses within the first metal and the second metal, depositing gate cap material within the recesses, and performing at least a third CMP process to remove excess portions of the deposited gate cap material.

20. The method of claim 19 , wherein the gate cap material comprises SiN.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Xu Peng

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title