Operating a memory device using a program order stamp to control a read voltage

Patent metadata

Field	Value
Publication number	US-9715341-B2
Application number	US-201514681389-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Oct 29, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A method is for operating a memory system including a memory device. The method includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device, and controlling a read voltage for performing a read operation on the memory device. The read voltage is controlled based on the program order information and a mapping table that stores a read voltage offset and a POS corresponding to the read voltage offset.

First claim

What is claimed is:

1. A method of operating a memory system comprising a memory device, the method comprising:
managing program order information of the memory device based on a program order stamp (POS) indicating a program order of program operations of a plurality of memory groups that are included in the memory device, wherein a POS is allocated to a memory group when a program operation is performed on the memory group, the POS being maintained until a next program operation is performed on the memory group; and
controlling a read voltage for performing a read operation on the memory device, based on the program order information and a mapping table that stores a read voltage offset and a POS corresponding to the read voltage offset,
wherein a value of the POS allocated to the memory group is changed when the next program operation is performed on the memory group, and
wherein a POS of value 1 is allocated to a memory group from among the plurality of memory groups on which a program operation is firstly performed, a POS of value 2 is allocated to a memory group on which a program operation is secondly performed, and a POS of value n is allocated to a memory group on which a program operation is nthly performed, wherein n is an integer greater than 2.

2. The method of claim 1 , wherein the controlling of the read voltage comprises:
generating the mapping table that stores the read voltage offset and the POS corresponding to the read voltage offset; and
variably determining the read voltage based on the mapping table and the program order information.

3. The method of claim 1 , wherein the plurality of memory groups are divided according to memory blocks, a POS is allocated according to the memory blocks, and the mapping table stores the read voltage offset and the POS according to the memory blocks.

4. The method of claim 3 , wherein the controlling of the read voltage comprises:
when read operations of a first address and a second address that are included in a same block are sequentially performed, determining a read voltage of the first address as a first voltage by referring to the mapping table and the program order information; and then
determining a read voltage of the second address as the first voltage without referring to the mapping table and the program order information.

5. The method of claim 1 , wherein the plurality of memory groups are divided according to word lines, a POS is allocated according to the word lines, and the mapping table stores the read voltage offset and the POS corresponding to the read voltage offset according to the word lines.

6. The method of claim 5 , wherein the controlling of the read voltage comprises:
when read operations of a first page and a second page that are stored at a same word line are sequentially performed, determining a read voltage of the first page as a first voltage based on the mapping table and the program order information; and then
determining a read voltage of the second page as the first voltage without referring to the mapping table and the program order information.

7. The method of claim 1 , wherein the read voltage offset comprises at least one offset having a fixed value irrespective of the memory device.

8. The method of claim 1 , wherein the read voltage offset comprises at least one offset having a value that varies according to the memory device.

9. The method of claim 1 , wherein the mapping table is generated according to dies, memory blocks, word lines, pages, or data types.

10. The method of claim 1 , wherein the mapping table is shared by at least two dies, at least two memory blocks, at least two word lines, at least two pages, or at least two data types.

11. The method of claim 1 , wherein the memory system further comprises a memory controller,
wherein the mapping table is stored in the memory device or is temporarily stored in the memory controller, and
the program order information is stored in the memory device.

12. The method of claim 1 , wherein the managing program order information comprises at least one of:
sequentially storing POSs according to addresses of the plurality of memory groups in order to search for the POSs according to the addresses of the plurality of memory groups; and
storing addresses of memory groups corresponding to POSs according to POSs that are sequentially increased in order to search for the addresses of the plurality of memory groups according to the POSs that are sequentially increased.

13. A method of operating a memory system comprising a memory device, the method comprising:
managing program order information of the memory device based on a program order stamp (POS) indicating a program order of relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device; and
controlling a read voltage for performing a read operation on the memory device, based on the program order information and a mapping table that stores a read voltage offset and a POS corresponding to the read voltage offset,
wherein the controlling of the read voltage comprises
generating the mapping table that stores the read voltage offset and the POS corresponding to the read voltage offset, and
variably determining the read voltage based on the mapping table and the program order information, and
wherein the generating of the mapping table comprises
if a read-out fails after the read operation is performed at a default level on a first memory group from among the plurality of memory groups, performing the read operation at a first level that is lower by a first offset than the default level and
if the read-out succeeds after the read operation is performed at the first level, mapping a POS corresponding to the first memory group to a first POS corresponding to the first offset.

14. The method of claim 13 , wherein the generating of the mapping table further comprises:
if the read-out fails after the read operation is performed at the first level on the first memory group, performing the read operation at a second level that is lower by a second offset than the default level; and
if the read-out succeeds after the read operation is performed at the second level, mapping the POS corresponding to the first memory group to a second POS corresponding to the second offset,
wherein a magnitude of the second offset is greater than a magnitude of the first offset.

15. The method of claim 13 , wherein the variably determining the read voltage comprises:
comparing a current POS corresponding to a second memory group to be currently read from among the plurality of memory groups with the first POS;
if the current POS is greater than the first POS, determining a read voltage of the second memory group as the default level; and
if the current POS is not greater than the first POS, determining the read voltage of the second memory group as the first level.

16. The method of claim 15 , further comprising:
if a read-out fails after the read operation is performed at the default level on the second memory group, performing the read operation on the second memory group at the first level; and
if the read-out succeeds after the read operation is performed on the second memory group at the first level, updating the first POS to the current POS.

17. The method of claim 16 , further comprising:
if a read-out fails after the read operation is performed at the first level on the second memory group, performing the read operation on the second memory group at a second level that is lower by a second offset than

Assignees

• Kim Kyung-Ryun
• Yoon Sang-Yong
• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun
• Yoon Sang-Yong

Classifications

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title