Method and apparatus for refresh programming of memory cells based on amount of threshold voltage downshift

Patent metadata

Field	Value
Publication number	US-9595342-B2
Application number	US-201514600365-A
Country	US
Kind code	B2
Filing date	Jan 20, 2015
Priority date	Jan 20, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Techniques are provided for periodically monitoring and adjusting the threshold voltage levels of memory cells in a charge-trapping memory device. When a criterion is met, such as based on the passage of a specified time period, the memory cells are read to classify them into different subsets according to an amount of downshift in threshold voltage (Vth). Two or more subsets can be used per data state. A subset can also comprise cells which are corrected using Error Correction Code (ECC) decoding. The subsets of memory cells are refresh programmed, without being erased, in which a Vth upshift is provided in proportion to the Vth downshift. The refresh programming can use a fixed or adaptive number of program pulses per subset. Some cells will have no detectable Vth downshift or a minor amount of Vth downshift which can be ignored. These cells need not be refresh programmed.

First claim

What is claimed is:

1. A method for operating a memory device, comprising:
performing a full programming operation involving a set of memory cells, the full programming operation programs memory cells using an initial verify voltage of one target data state;
after completion of the full programming operation, making a determination of whether a criterion is met for checking a data retention of the set of memory cells;
in response to the determination that the criterion is met, performing sensing operations for memory cells of the one target data state to identify, in the set of memory cells, a plurality of subsets of memory cells comprising first, second and third subsets of memory cells, the first subset of memory cells is in a first threshold voltage range which encompasses the initial verify voltage, the second subset of memory cells is in a second threshold voltage range below the first threshold voltage range, and the third subset of memory cells is in a third threshold voltage range below the second threshold voltage range wherein the identifying the plurality of subsets of memory cells comprises identifying the first subset of memory cells by providing a first bit combination in latches of the first subset of memory cells, identifying the second subset of memory cells by providing a second bit combination in latches of the second subset of memory cells, and identifying the third subset of memory cells by providing a third bit combination in latches of the third subset of memory cells; and
performing refresh programming for the second subset of memory cells and refresh programming for the third subset of memory cells but not for the first subset of memory cells, wherein a threshold voltage upshift of the third subset of memory cells due to the refresh programming for the third subset of memory cells is larger than a threshold voltage upshift of the second subset of memory cells due to the refresh programming for the second subset of memory cells wherein:
the performing the refresh programming for the second subset of memory cells comprises programming each memory cell of the second subset of memory cells using one or more program pulses until the second subset of memory cells passes an associated verify test; and
the performing the refresh programming for the third subset of memory cells comprises programming each memory cell of the third subset of memory cells using one or more program pulses until the third subset of memory cells passes an associated verify test, wherein a verify voltage of the associated verify test of the third subset of memory cells is higher than a verify voltage of the associated verify test of the second subset of memory cells.

2. The method of claim 1 , wherein:
the first threshold voltage range encompasses the initial verify voltage and a range of voltages below the initial verify voltage.

3. The method of claim 1 , wherein:
the performing the refresh programming for the second subset of memory cells comprises programming each memory cell of the second subset of memory cells using a first program pulse and without performing an associated verify test or further programming of the second subset of memory cells; and
the performing the refresh programming for the third subset of memory cells comprises programming each memory cell of the third subset of memory cells using the first program pulse and a second program pulse and without performing an associated verify test or further programming of the third subset of memory cells.

4. The method of claim 1 , wherein:
the performing the refresh programming for the second subset of memory cells comprises programming each memory cell of the second subset of memory cells using a first program pulse and without performing an associated verify test or further programming of the second subset of memory cells.

5. The method of claim 1 , wherein:
the performing the refresh programming for the third subset of memory cells comprises programming each memory cell of the third subset of memory cells using one or more program pulses until the third subset of memory cells passes an associated verify test.

6. The method of claim 5 , wherein:
the associated verify test of the third subset of memory cells uses a verify voltage (VvA 3 , VvB 3 , VvC 3 ) which is higher than the initial verify voltage.

7. The method of claim 6 , wherein:
the full programming operation programs memory cells in the set of memory cells to a plurality of target data states; and
the verify voltage of the associated verify test of the third subset of memory cells is higher than the initial verify voltage by an amount which is relatively greater when the one target data state is a relatively higher target data state among the plurality of target data states.

8. The method of claim 1 , wherein the plurality of subsets comprises a fourth subset of memory cells, the fourth subset of memory cells is in a fourth threshold voltage range which is below the third threshold voltage range, and the fourth subset of memory cells is corrected using error correction code decoding, the method further comprising:
performing refresh programming for the fourth subset of memory cells, wherein a threshold voltage upshift of the fourth subset of memory cells due to the refresh programming for the fourth subset of memory cells is larger than the threshold voltage upshift of the third subset of memory cells due to the refresh programming for the third subset of memory cells.

9. The method of claim 1 , wherein:
the criterion is met for checking the data retention of the memory cells of the one target data state based on passage of a specified time period.

10. The method of claim 1 , further comprising:
obtaining a count of memory cells in one or more subsets of the plurality of subsets of memory cells; and
if the count is above a threshold, performing refresh programming for memory cells of another target data state, below the one target data state, in response to the determination that the criterion is met; and
if the count is not above the threshold, not performing refresh programming for the memory cells of another target data state in response to the determination that the criterion is met.

11. A memory device, comprising:
a set of memory cells; and
a control circuit, the control circuit is configured to:
perform a full programming operation involving the set of memory cells, the full programming operation programs memory cells to a plurality of target data states, the plurality of target data states comprise a relatively high target data state having an associated verify voltage and a relatively low target data state having an associated verify voltage;
determine that a criterion is met for checking a data retention of the set of memory cells;
when the criterion is met: (a) identify a number N1>1 of subsets of memory cells which were programmed to the relatively high target data state and which have a threshold voltage below the verify voltage of the relatively high target data state, each subset of the N1 subsets is associated with a different threshold voltage range among N1 adjacent threshold voltage ranges, wherein to identify the number N1>1 of subsets of memory cells the control circuit is configured to update latches of the number N1>1 of subsets of memory cells and (b) identify a number N2>=1 of subsets of memory cells which were programmed to the relatively low target data state and which have a threshold voltage below the verify voltage of the relatively low target data state, wherein N2<N1 and, to identify the number N2>=1 of subsets of memory cells, the control circuit is configured to update latches of the number N2>=1 of subsets of memory cells, wh

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Pang Liang
• Dong Yingda
• Chen Jian

Classifications

• G11C11/5621 Primary

  using charge storage in a floating gate · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title