Memory system and method including determining a read voltage based on program order information and a plurality of mapping tables

Patent metadata

Field	Value
Publication number	US-9921749-B2
Application number	US-201514743458-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Oct 29, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method of operating a memory system, including a memory device, includes managing program order information of the memory device based on a program order stamp (POS) indicating a relative temporal relationship between program operations of a plurality of memory groups that are included in the memory device. The method includes generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially decreased or reduced, and generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by using a plurality of voltage levels that are sequentially increased. A read voltage for performing a read operation on the memory device is variably determined based on the first and second mapping tables and the program order information.

First claim

What is claimed is:

1. A method of operating a memory system comprising a memory device, the method comprising:
managing program order information of the memory device based on a program order stamp (POS) indicating a program order of program operations of a plurality of memory groups that are included in the memory device;
generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by performing a sequence of read operations on the memory device using a plurality of read voltage levels that are sequentially reduced;
generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by performing a sequence of read operations on the memory device using a plurality of read voltage levels that are sequentially increased; and
variably determining a read voltage for performing a read operation on the plurality of memory groups, based on the first and second mapping tables and the program order information,
wherein a POS of value 1 is allocated to a memory group from among the plurality of memory groups on which a program operation is firstly performed, a POS of value 2 is allocated to a memory group on which a program operation is secondly performed, and a POS of value n is allocated to a memory group on which a program operation is nthly performed, wherein n is an integer greater than 2.

2. The method of claim 1 , wherein the upper POS is determined to be close to an upper bound level of a read voltage range, and the lower POS is determined to be close to a lower bound level of the read voltage range.

3. The method of claim 1 , wherein the generating of the first mapping table comprises:
when read-out fails after a read operation is performed using a read voltage level at a default level on a first memory group from among the plurality of memory groups, performing a read operation at a first level that is lower than the default level by a first read voltage offset; and
when read-out succeeds after a read operation is performed at the first level, mapping a POS corresponding to the first memory group to a first upper POS corresponding to the first read voltage offset.

4. The method of claim 3 , wherein the generating of the first mapping table further comprises:
when read-out fails after a read operation is performed at the first level on the first memory group, performing a read operation at a second level that is lower than the default level by a second read voltage offset; and
when read-out succeeds after a read operation is performed at the second level, mapping the POS corresponding to the first memory group to a second upper POS corresponding to the second read voltage offset;
wherein a magnitude of the second read voltage offset is greater than a magnitude of the first read voltage offset.

5. The method of claim 1 , wherein the generating of the second mapping table comprises:
when read-out fails after a read operation is performed using a read voltage level at a second level that is lower by a second read voltage offset than a default level on a first memory group from among the plurality of memory groups, performing a read operation at a first level that is lower than the default level by a first read voltage offset; and
when read-out succeeds after a read operation is performed at the first level, mapping a POS corresponding to the first memory group to a second lower POS corresponding to the second read voltage offset;
wherein a magnitude of the second read voltage offset is greater than a magnitude of the first read voltage offset.

6. The method of claim 5 , wherein the generating of the second mapping table further comprises:
when read-out fails after a read operation is performed at the first level on the first memory group, performing a read operation at the default level; and
when read-out succeeds after a read operation is performed at the default level, mapping the POS corresponding to the first memory group to a first lower POS corresponding to the first read voltage offset.

7. The method of claim 1 , further comprising generating a third mapping table that stores the read voltage offset and a middle POS corresponding to an average value between the upper POS and the lower POS corresponding to the read voltage offset, based on the first and second mapping tables;
wherein variably determining the read voltage comprises variably determining the read voltage based on the first through third mapping tables and the program order information.

8. The method of claim 1 , wherein the plurality of memory groups are divided according to memory blocks, the upper and lower POSs are allocated according to the memory blocks, and the first and second mapping tables respectively store the read voltage offset and the upper and lower POSs according to the memory blocks.

9. The method of claim 1 , wherein the plurality of memory groups are divided according to word lines, the upper and lower POSs are allocated according to the word lines, and the first and second mapping tables respectively store the read voltage offset and the upper and lower POSs according to the word lines.

10. A method of operating a memory system comprising a memory device, the method comprising:
managing program order information of the memory device based on a program order stamp (POS) indicating a program order of program operations of a plurality of memory groups that are included in the memory device;
generating a first mapping table that stores a read voltage offset and an upper POS corresponding to the read voltage offset, by performing a sequence of read operations on the memory device using a plurality of read voltage levels that are sequentially reduced;
generating a second mapping table that stores the read voltage offset and a lower POS corresponding to the read voltage offset, by performing a sequence of read operations on the memory device using a plurality of read voltage levels that are sequentially increased;
generating a third mapping table that stores the read voltage offset and a middle POS corresponding to an average value between the upper POS and the lower POS corresponding to the read voltage offset, based on the first and second mapping tables; and
variably determining a read voltage for performing a read operation on the plurality of memory groups, based on the first through third mapping tables and the program order information,
wherein variably determining the read voltage comprises:
comparing a current POS corresponding to a second memory group to be currently read from among the plurality of memory groups with a first middle POS corresponding to a first read voltage offset;
when the current POS is not less than the first middle POS, determining a read voltage of the second memory group as a default level; and
when the current POS is less than the first middle POS, determining the read voltage of the second memory group as a first level that is lower than the default level by the first read voltage offset.

11. The method of claim 10 , further comprising:
when read-out fails after a read operation is performed using a read voltage level at the default level on the second memory group, performing a read operation at the first level;
when read-out fails after a read operation is performed at the first level on the second memory group, performing a read operation at a second level that is lower than the default level by a second read voltage offset; and
when read-out succeeds after a read operation is performed at the first level or the second level, updating the first and second mapping tables.

12. The method of claim 11 , wherei

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun
• Jang Joon-Suc

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title