Partial block read voltage offset
US-2024071506-A1 · Feb 29, 2024 · US
US9330775B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9330775-B2 |
| Application number | US-201414150320-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 8, 2014 |
| Priority date | Jan 14, 2013 |
| Publication date | May 3, 2016 |
| Grant date | May 3, 2016 |
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A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells.
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What is claimed is: 1. A method of operating a flash memory, the method comprising: counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range defined by a first reference read voltage for discriminating between a first pair of threshold voltage distributions adjacently located and a first search read voltage having a first voltage difference with the first reference read voltage; counting the number of memory cells having threshold voltages included in a second adjacent threshold voltage range defined by the first reference read voltage and a second search read voltage having a second voltage difference with the first reference read voltage; and setting a first optimal read voltage based on a count difference between the counted number of the memory cells having the threshold voltages included in the first adjacent threshold voltage range and the counted number of the memory cells having the threshold voltages included in the second adjacent threshold voltage range. 2. The method of claim 1 , wherein setting the first optimal read voltage based on the count difference, is performed by calculating using a result value generated from applying a first adjustment parameter to the count difference, wherein the first adjustment parameter is a constant regarding the count difference. 3. The method of claim 2 , wherein the first optimal read voltage has a voltage level that is shifted from the first reference read voltage by the result value. 4. The method of claim 2 , wherein the first pair of the threshold voltage distribution has the form of a Gaussian distribution, and the first adjustment parameter is independent of the standard deviation of the adjacently located threshold voltage distribution. 5. The method of claim 2 , wherein the first adjustment parameter is a coefficient of a first degree of an equation, the equation representing the relation between the difference between the number of memory cells having the threshold voltages included in the first adjacent threshold voltage range and the second adjacent threshold voltage range, and the difference between the first reference read voltage and the first optimal read voltage. 6. The method of claim 2 , wherein the first adjustment parameter is set differently according to the counted number of erasures of the memory cells having the threshold voltages within the first pair of the threshold voltage distributions. 7. The method of claim 2 , further comprising: counting the number of memory cells having threshold voltages included in a third threshold voltage range defined by the second reference read voltage for discriminating between a second pair of threshold voltage distributions adjacently located and a third search read voltage having a third voltage difference from the second reference read voltage, and counting the number of memory cells having threshold voltages included in a fourth threshold voltage range defined by the second reference read voltage and a fourth search read voltages having a fourth voltage difference from the second reference read voltage; and setting a second optimal read voltage based on a result value generated by applying a second adjustment parameter to a count difference between the number of memory cells having threshold voltages included in the third threshold voltage range and the number of memory cells having threshold voltages included in the fourth threshold voltage range. 8. The method of claim 7 , wherein the first adjustment parameter and the one second adjustment parameter are the same. 9. The method of claim 7 , wherein the first adjustment parameter is different from the second adjustment parameter. 10. The method of claim 1 , wherein the first pair of the threshold voltage distributions include an erasing state and a first program state. 11. The method of claim 1 , wherein the first pair of the threshold voltage distributions include two different program states. 12. The method of claim 1 , wherein the first pair of the threshold voltage distributions include the program state having a highest threshold voltage among threshold voltage distributions which are set for the flash memory. 13. The method of claim 1 , further comprises setting the first reference read voltage based on initial states of the first pair of the threshold voltage distributions before the counting the number of memory cells having threshold voltages included in the first adjacent threshold voltage range and the number of memory cells having threshold voltages included in the second adjacent threshold voltage range. 14. The method of claim 1 , wherein the first search read voltage and the second search read voltage are a pair of soft read voltages for the first pair of the threshold voltage distributions. 15. The method of claim 1 , wherein the first voltage difference and the second voltage difference are equal. 16. The method of claim 1 , wherein the first voltage difference is different from the second voltage difference. 17. The method of claim 1 , wherein the number of memory cells having the threshold voltages respectively included in the first adjacent threshold voltage range, and the second adjacent threshold voltage range are equal by the first optimal read voltage. 18. The method of claim 1 , wherein the flash memory is a three-dimensionally stacked vertical NAND flash memory. 19. A method of operating a multi-level cell NAND flash memory, the method comprising: respectively counting the number of memory cells having threshold voltages included in one or more a first adjacent threshold voltage range and a second adjacent voltage range defined by a first reference read voltage and a pair of first search read voltages having a first voltage difference and a second voltage difference from the a first reference read voltage, respectively; and setting a first optimal read voltage based on a result value generated by applying an first adjustment parameter to the difference between the number of memory cells having threshold voltages within the first adjacent threshold voltage range and the number of memory cells having threshold voltages within the second adjacent threshold voltage range. 20. The method of claim 19 , wherein the first adjustment parameter is a constant regarding the difference between the number of memory cells included in the first adjacent threshold voltage ranges and the second adjacent threshold voltage ranges, and is independent of a standard deviation of adjacently located threshold voltage distributions which include the first adjacent threshold voltage ranges and the second adjacent threshold voltage ranges and are formed as a Gaussian distributions. 21. A method of operating a multi-level cell NAND flash memory system, the method comprising: counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range defined by a first reference read voltage and one of a pair of first search read voltages having a, first voltage difference and a second voltage difference from the first reference read voltages, respectively; counting the number of memory cells having threshold voltages included in a second adjacent threshold voltage range defined by the first reference read voltage and the other one of the pair of first search read voltages; and setting a first optimal read voltage based on a result value generated by applying an adjustment parameter to the difference between the number of memory cells having thresh
using differential sensing or reference cells, e.g. dummy cells · CPC title
comprising cells having several storage transistors connected in series · CPC title
Sensing or reading circuits; Data output circuits · CPC title
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title
using variable threshold transistors, e.g. FAMOS · CPC title
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