Memory system and method of operating same using program order information

Patent metadata

Field	Value
Publication number	US-9858014-B2
Application number	US-201514666476-A
Country	US
Kind code	B2
Filing date	Mar 24, 2015
Priority date	Oct 29, 2014
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information.

First claim

What is claimed is:

1. A method of operating a memory system comprising a memory device, the method comprising:
managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device; and
controlling operations directed to the plurality of memory groups in response to the program order information,
wherein the controlling of operations comprises at least one of:
controlling selection of a read voltage for each one of the plurality of memory groups based on the program order information,
controlling a reclaim operation performed on at least one of the plurality of memory groups based on the program order information;
controlling a garbage collection operation performed on the memory device based on the program order information; and
controlling a wear leveling operation performed on the memory device based on the program order information.

2. The method of claim 1 , wherein the POSs indicate an order at least one of erase operations and program operations performed in relation to the plurality of memory groups.

3. The method of claim 1 , wherein the managing of the program order information comprises sequentially storing the POSs according to addresses of the plurality of memory groups, such that the POSs are searchable according to the addresses of the plurality of memory groups.

4. The method of claim 1 , wherein the managing of the program order information comprises storing addresses of the plurality of memory groups corresponding to sequentially increasing POSs, such that the addresses of the memory groups are searchable according to the POSs.

5. The method of claim 1 , wherein the managing of the program order information comprises storing the program order information using at least one of a table, a linked list, a doubly-linked list, a circular buffer, and a first-in first-out (FIFO) buffer.

6. The method of claim 1 , wherein the plurality of memory groups is designated in the memory device in accordance with memory block units.

7. The method of claim 6 , wherein the managing of the program order information comprises at least one of:
allocating a POS to a memory block and updating the program order information when a program operation directed to the memory block begins,
allocating a POS to a memory block and updating the program order information when a program operation directed to the memory block is completed, and
allocating a POS to a memory block and updating the program order information when an erase operation is performed on the memory block.

8. The method of claim 1 , wherein the plurality of memory groups is designated in the memory device in accordance with word line units.

9. The method of claim 8 , wherein the managing of the program order information comprises at least one of:
allocating a POS to a first word line and updating the program order information when a first-executed program operation directed to the first word line is executed, and
allocating a POS to a first word line and updating the program order information when a last-executed program operation directed to the first word line is executed.

10. The method of claim 1 , wherein the memory device comprises a single-level memory cell (SLC) block and a multi-level memory cell (MLC) block, and
managing of the program order information comprises managing the program order information for only the MLC block.

11. The method of claim 1 , wherein the memory device comprises a multi-level memory cell (MLC) block, and
managing the program order information comprises respectively managing first program order information for the MLC block and managing second program order information for the MLC block.

12. The method of claim 1 , wherein at least two of the plurality of memory groups share a same POS.

13. The method of claim 1 , further comprising:
storing the program order information in the memory device.

14. The method of claim 13 , wherein the program order information comprises a flag and a POS of each one of the plurality of memory groups, the flag indicating whether the memory group is used in order to update a mapping table stores a read voltage offset and a POS corresponding to the read voltage offset.

15. The method of claim 1 , wherein the controlling of the selection of a read voltage comprises:
searching for a POS corresponding to a first memory group among the plurality of memory groups based on the program order information;
searching for a read voltage offset corresponding to the POS corresponding to the first memory group; and
performing a read operation directed to the first memory group using the read voltage offset.

16. The method of claim 1 , wherein the controlling of the reclaim operation comprises at least one of;
performing the reclaim operation directed to a first memory group among the plurality of memory groups having an allocated POS, and
performing the reclaim operation on at least one memory group having to a POS less than or equal to a critical value.

17. A method of operating a memory system comprising a memory device, the method comprising:
based on program order stamps (POSs) indicating relative temporal relationship between program operations performed on a plurality of memory groups that are included in the memory device, generating program order information that sequentially contains the POSs according to addresses of the plurality of memory groups; and
controlling operations performed on the plurality of memory groups based on the program order information,
wherein the controlling of operations directed to the plurality of memory groups in response to the program order information comprises at least one of:
controlling selection of a read voltage for each one of the plurality of memory groups based on the program order information,
controlling a reclaim operation performed on at least one of the plurality of memory groups based on the program order information;
controlling a garbage collection operation performed on the memory device based on the program order information; and
controlling a wear leveling operation performed on the memory device based on the program order information.

18. A method of operating a memory system comprising a memory device, the method comprising:
based on program order stamps (POSs) indicating relative temporal relationships between program operations performed on a plurality of memory groups that are included in the memory device, generating program order information that contains addresses of memory groups corresponding to POSs that are sequentially increased according to the POSs that are sequentially increased; and
controlling operations performed on the plurality of memory groups based on the program order information,
wherein the controlling of operations directed to the plurality of memory groups in response to the program order information comprises at least one of:
controlling selection of a read voltage for each one of the plurality of memory groups based on the program order information,
controlling a reclaim operation performed on at least one of the plurality of memory groups based on the program order information;
controlling a garbage collection operation performed on the memory device based on the program order information; and
controlling a wear leveling operation performed on the memory device based on the program order information.

19. The method of claim 18

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Ryun

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title