Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice

Patent metadata

Field	Value
Publication number	US-11355667-B2
Application number	US-201916380091-A
Country	US
Kind code	B2
Filing date	Apr 10, 2019
Priority date	Apr 12, 2018
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an active device layer on the superlattice comprising at least one active semiconductor device.

First claim

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a plurality of waveguides on a substrate;
forming a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming an active device layer on the superlattice comprising at least one active semiconductor device.

2. The method of claim 1 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

3. The method of claim 1 further comprising forming a plurality of optical modulator regions within the superlattice.

4. The method of claim 3 further comprising forming vias extending through the active device layer to the optical modulator regions.

5. The method of claim 3 further comprising planarizing the superlattice layer after forming the optical modulator regions.

6. The method of claim 3 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

7. The method of claim 1 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

8. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

9. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

10. A method for making a semiconductor device comprising:
forming a plurality of waveguides on a semiconductor-on-insulator (SOI) substrate;
forming a superlattice overlying the SOI substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a plurality of optical modulator regions within the superlattice; and
forming an active device layer on the superlattice comprising at least one active semiconductor device.

11. The method of claim 10 further comprising forming vias extending through the active device layer to the optical modulator regions.

12. The method of claim 10 further comprising planarizing the superlattice layer after forming the optical modulator regions.

13. The method of claim 10 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

14. The method of claim 10 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

15. The method of claim 10 wherein the base semiconductor monolayers comprise silicon.

16. The method of claim 10 wherein the at least one non-semiconductor monolayer comprises oxygen.

17. A method for making a semiconductor device comprising:
forming a plurality of waveguides on a substrate;
forming a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and
forming an active device layer on the superlattice comprising at least one active semiconductor device.

18. The method of claim 17 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate.

19. The method of claim 17 further comprising forming a plurality of optical modulator regions within the superlattice.

20. The method of claim 19 further comprising forming vias extending through the active device layer to the optical modulator regions.

21. The method of claim 19 further comprising planarizing the superlattice layer after forming the optical modulator regions.

22. The method of claim 19 wherein forming the optical modulator regions comprises implanting a dopant to define the optical modulator regions.

23. The method of claim 17 wherein the at least one active semiconductor device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

Assignees

• Atomera Inc

Inventors

• Stephenson Robert John

Classifications

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D62/8162

  having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation · CPC title

• H10H20/811

  having quantum effect structures or superlattices, e.g. tunnel junctions · CPC title