Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11257841-B2
Application number	US-202016787195-A
Country	US
Kind code	B2
Filing date	Feb 11, 2020
Priority date	Apr 10, 2019
Publication date	Feb 22, 2022
Grant date	Feb 22, 2022

Abstract

A three-dimensional semiconductor memory device including a stack structure including gate structures and first dielectric patterns alternately stacked, a vertical channel penetrating the stack structure, and a charge storage layer extending from between the vertical channel and the first gate structures to between the vertical channel and the first dielectric patterns. The gate structures include first gate structures having a top surface and a bottom surface facing each other and having different width. The charge storage layer includes first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns. A thickness of the first segments is greater than a thickness of the second segments. One of the width of the top surface and the width of bottom surface of each first gate structure is the same as that of a first dielectric pattern on the first gate structure.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a stack structure including a plurality of gate structures and first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structures including a plurality of first gate structures, and each of the first gate structures:
having a top surface and a bottom surface that faces the top surface,
having a width of the top surface that is different than a width of the bottom surface,
a first gate part, and
a second gate part between the first gate part and the first dielectric pattern on the first gate structure, wherein the second gate part includes a region in which a width of the second gate part decreases as approaching the first dielectric pattern;

a vertical channel penetrating the stack structure on the substrate; and
a charge storage layer extending from a first location between the vertical channel and the first gate structures to a second location between the vertical channel and the first dielectric patterns, the charge storage layer including first segments between the vertical channel and the first gate structures, and second segments between the vertical channel and the first dielectric patterns, wherein:
a thickness of the first segments is greater than a thickness of the second segments in a direction parallel to a top surface of the substrate, and
the width of the top surface or the width of the bottom surface of each first gate part is the same as a width of a first dielectric pattern, among the first dielectric patterns, on the top surface of the first gate structure.

2. The three-dimensional semiconductor memory device of claim 1 , wherein:
the width of the top surface of each first gate structure is less than the width of the bottom surface of the first gate structure, and
the width of the top surface of each first gate structure is less than a width of a top surface of the first dielectric pattern on the first gate structure.

3. The three-dimensional semiconductor memory device of claim 1 , wherein:
the gate structures further include a second gate structure,
the first gate structures and the second gate structure constitute a single cell string,
the first gate structures are cell gate structures of the single cell string, and
the second gate structure is a string select gate structure of the single cell string.

4. The three-dimensional semiconductor memory device of claim 1 , wherein:
each first gate structure includes a first gate part and a second gate part between the first gate part and the first dielectric pattern on the first gate structure,
at each first gate structure the charge storage layer has a depression which is recessed from a sidewall of the charge storage layer, and
the depression is disposed at a same height above a top surface of the substrate as the second gate part.

5. The three-dimensional semiconductor memory device of claim 1 , further comprising:
a tunnel dielectric layer between the charge storage layer and the vertical channel; and
a blocking dielectric layer between the charge storage layer and the first gate structures, wherein:
at each first gate structure, the blocking dielectric layer has a first cavity which is depressed from a sidewall of the blocking dielectric layer,
the charge storage layer has a second cavity which is depressed from a sidewall of the charge storage layer,
the charge storage layer is in the first cavity, and
the tunnel dielectric layer is in the second cavity.

6. The three-dimensional semiconductor memory device of claim 5 , further comprising a capping pattern between the vertical channel and the tunnel dielectric layer at each first gate structure, the capping pattern being in the second cavity.

7. The three-dimensional semiconductor memory device of claim 1 , wherein:
the substrate includes a cell array region and a pad region,
the stack structure extends onto the pad region from the cell array region, and
the three-dimensional semiconductor memory device further comprises a first dummy vertical structure and a second dummy vertical structure which penetrate the stack structure on the pad region of the substrate,
the first dummy vertical structure has first protrusions which protrude from a sidewall of the first dummy vertical structure,
the second dummy vertical structure has second protrusions which protrude from a sidewall of the second dummy vertical structure, and
the first protrusions of the first dummy vertical structure and the second protrusions of the second dummy vertical structure are in contact with the first gate structures.

8. The three-dimensional semiconductor memory device of claim 7 , wherein the first protrusions of the first dummy vertical structure are in contact with the second protrusions of the second dummy vertical structure.

9. The three-dimensional semiconductor memory device of claim 7 , further comprising:
respective air gaps between the first protrusions of the first dummy vertical structure and the second protrusions of the second dummy vertical structure, wherein
the air gaps are interposed between the first dielectric patterns and the first gate structures.

10. The three-dimensional semiconductor memory device of claim 1 , wherein the first gate structures are adjacent to each other in a direction perpendicular to a top surface of the substrate.

11. The three-dimensional semiconductor memory device of claim 1 , wherein:
the charge storage layer surrounds the vertical channel,
the gate structures surround the charge storage layer, and
a shape of the first gate structures is the same at opposite sides of the vertical channel.

12. A three-dimensional semiconductor memory device comprising:
a stack structure including a plurality of gate structures and first dielectric patterns alternately and repeatedly stacked on a substrate, the gate structures including a plurality of first gate structures each having a top surface and a bottom surface that faces the top surface and a width of the top surface that is different than a width of the bottom surface;
a vertical channel penetrating the stack structure on the substrate; and
a charge storage structure extending from a first location between the vertical channel and the first gate structures to a second location between the vertical channel and the first dielectric patterns, the charge storage structure including first charge storage segments between the vertical channel and the first gate structures and second charge storage segments between the vertical channel and the first dielectric patterns, wherein:
a thickness of the first charge storage segment is greater than a thickness of the second charge storage segment,
the width of the top surface or the width of the bottom surface of each first gate structure is the same as a width of a first dielectric pattern on the top surface of the first gate structure, and
the width of the bottom surface of each first gate structure is less than the width of the top surface of the first gate structure, and
the width of the bottom surface of each first gate structure is less than a width of a bottom surface of the first dielectric pattern on the first gate structure.

13. The three-dimensional semiconductor memory device of claim 12 , wherein the charge storage structure covers horizontal surfaces of the first dielectric patterns, the horizontal surfaces being exposed to areas where the first dielectric patterns are spaced apart from the first gate structures.

14. The three-dimensional semiconductor memory device of claim 12 , wherein:
the width of the top surface of each first gate st

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Jin-Kyu
• Jang Woojae
• Lee Changsub
• Park Sejun
• Lee Jaeduk
• Lee Jung Hoon

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D64/514 Primary

  characterised by the insulating layers · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title