Three dimensional NAND device having a wavy charge storage layer

Patent metadata

Field	Value
Publication number	US-9553146-B2
Application number	US-201414297106-A
Country	US
Kind code	B2
Filing date	Jun 5, 2014
Priority date	Jun 5, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.

First claim

What is claimed is:

1. A monolithic three dimensional NAND string, comprising:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;
a stack of alternating first layers and second layers, wherein the alternating second layers include a plurality of control gate electrodes which extend substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprises at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level, and wherein the alternating first layers comprise an insulating material and include an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;
an opening vertically extending through the stack of alternating first layers and second layers and including a blocking dielectric layer located in contact with the plurality of control gate electrodes and the interlevel insulating layer; a charge storage layer located at least partially in contact with the blocking dielectric layer, and wherein the charge storage layer comprises at least a first charge storage segment located in the first device level, a second charge storage segment located in the second device level, and a third charge storage segment located adjacent to the interlevel insulating layer between the first device level and the second device level; and a tunnel dielectric located between the charge storage layer and the semiconductor channel;
a first source or drain electrode located directly on the major surface of the substrate and laterally extending underneath an entirety of the opening and underneath the stack of alternating first layers and second layers; and
a second source or drain electrode overlying the stack of alternating first layers and second layers and laterally extending over an entirety of the opening,
wherein the charge storage layer has a curved profile along at least one of the first charge storage segment and the third charge storage segment;
wherein the blocking dielectric layer, the charge storage layer and the tunnel dielectric are directly in contact with a major surface of the first source or drain electrode; and
wherein a bottom surface of the second source or drain electrode is directly in contact with the blocking dielectric layer, the charge storage layer and the tunnel dielectric.

2. The monolithic three dimensional NAND string of claim 1 , wherein the charge storage layer has a first curved profile along the first charge storage segment and a second curved profile along the third charge storage segment, wherein the second curved profile is different from the first curved profile.

3. The monolithic three dimensional NAND string of claim 2 , wherein the first curved profile is convex in the direction of the first control gate electrode and the second curved profile is concave in the direction of the interlevel insulating layer.

4. The monolithic three dimensional NAND string of claim 2 , wherein the charge storage layer has a substantially uniform thickness.

5. The monolithic three dimensional NAND string of claim 1 , wherein the charge storage layer is continuous.

6. The monolithic three dimensional NAND string of claim 1 , wherein the blocking dielectric layer has a complementary curved profile along at least one segment in contact with the charge storage layer.

7. The monolithic three dimensional NAND string of claim 6 , wherein the blocking dielectric layer has a substantially uniform thickness.

8. The monolithic three dimensional NAND string of claim 6 , wherein each control gate electrode of the plurality of control gate electrodes contacting the blocking dielectric layer has a complementary curved profile.

9. The monolithic three dimensional NAND string of claim 1 , wherein the tunnel dielectric has a complementary curved profile along at least one segment in contact with the charge storage layer.

10. The monolithic three dimensional NAND string of claim 9 , wherein the tunnel dielectric has a substantially uniform thickness.

11. The monolithic three dimensional NAND string of claim 9 , wherein the semiconductor channel has a complementary curved profile along at least one segment in contact with the tunnel dielectric.

12. The monolithic three dimensional NAND string of claim 11 , further comprising an insulating core fill layer contacting the semiconductor channel.

13. The monolithic three dimensional NAND string of claim 12 , wherein:
the semiconductor channel is a hollow quasi-cylindrical body having walls with a substantially uniform thickness, and
the insulating core fill layer is located inside the hollow quasi-cylindrical body and has a variable thickness in a direction perpendicular to the major surface of the substrate.

14. The monolithic three dimensional NAND string of claim 1 , wherein the charge storage layer has a wavy profile.

15. The monolithic three dimensional NAND string of claim 14 , wherein blocking dielectric layer, the tunnel dielectric, and the semiconductor channel each have a complementary wavy profile to the charge storage layer.

16. The monolithic three dimensional NAND string of claim 1 , wherein:
the charge storage layer comprises silicon nitride;
the tunnel dielectric comprises silicon oxide, silicon oxynitride or a combination of silicon oxide and silicon nitride; and
the blocking dielectric layer comprises silicon oxide.

17. The monolithic three dimensional NAND string of claim 1 ,
wherein the semiconductor channel has a pillar shape and extends substantially perpendicular to the major surface of the substrate; and
wherein the second source or drain electrode contacts the pillar-shaped semiconductor channel from above, and the first source or drain electrode contacts the pillar-shaped semiconductor channel from below.

18. The monolithic three dimensional NAND string of claim 1 , wherein the electrode contacts a top surface of a topmost layer among the stack of alternating first layers and second layers.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Baenninger Matthias
• Matsudaira Akira
• Lee Yao-Sheng
• Alsmeier Johann

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L29/1029 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10D62/221 Primary

  of FETs · CPC title