Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9653565-B2
Application number	US-201514865078-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 29, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.

First claim

What is claimed is:

1. A three dimensional semiconductor memory device comprising:
a vertical channel structure extending in a vertical direction on a substrate;
interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate;
gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent the vertical channel structure being rounded;
a vertical insulating layer extending in the vertical direction between the vertical channel structure and the gate electrodes and between the vertical channel structure and the interlayer insulating layers; and
auxiliary gate insulating patterns disposed between the corners of the gate electrodes and the vertical insulating layer,
wherein side surfaces of the auxiliary gate insulating patterns are substantially coplanar with side surfaces of the interlayer insulating layers in the vertical direction on the substrate,
wherein a top surface of a respective one of the auxiliary gate insulating patterns is substantially coplanar with a to surface of a respective one of the gate electrodes adjacent the respective one of the auxiliary gate insulating patterns,
wherein the top surface of the respective one of the auxiliary gate insulating patterns is a surface of the respective one of the auxiliary gate insulating patterns that is furthest from the substrate, and
wherein the top surface of the respective one of the gate electrodes is a surface of the respective one of the gate electrodes that is furthest from the substrate.

2. The device of claim 1 , wherein the auxiliary gate insulating patterns are vertically arranged along an outer sidewall of the vertical channel structure.

3. The device of claim 1 , further comprising a semiconductor pattern between the vertical channel structure and the substrate, wherein the semiconductor pattern is surrounded by a lowest one of the gate electrodes.

4. The device of claim 3 , wherein the semiconductor pattern is in contact with the vertical channel structure and the vertical channel structure is electrically connected to the substrate through the semiconductor pattern.

5. The device of claim 1 , wherein the vertical channel structure is configured to store charges of a first polarity, and
wherein the auxiliary gate insulating patterns comprise a material having fixed charges of a second polarity configured to repel the charges of the first polarity in portions of the vertical channel structure that are adjacent the auxiliary gate insulating patterns.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Jang Byong-Hyun
• Yoo Dongchul
• Ahn Jaeyoung
• Lim Hunhyeong

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L29/495 Primary

  Electricity · mapped topic

• H10D64/665 Primary

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10B41/30 Primary

  characterised by the memory core region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title