Three-dimensional memory device with partially discrete charge storage regions and method of making thereof

Patent metadata

Field	Value
Publication number	US-9960180-B1
Application number	US-201715470453-A
Country	US
Kind code	B1
Filing date	Mar 27, 2017
Priority date	Mar 27, 2017
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film,
wherein the memory film comprises:
a continuous charge trapping material layer comprising a dielectric first charge trapping material and extending through multiple electrically conductive layers within the alternating stack; and
discrete charge trapping material portions comprising a dielectric second charge trapping material and located at levels of the electrically conductive layers, vertically separated from each other, and contacting an outer sidewall of the continuous charge trapping material layer.

2. The three-dimensional memory device of claim 1 , wherein the first charge trapping material and the second charge trapping material comprise silicon nitride having the same or different composition.

3. The three-dimensional memory device of claim 1 , wherein each of the discrete charge trapping material portions comprise annular portions which contact a planar bottom surface of an overlying one of the insulating layers and a planar top surface of an underlying one of the insulating layers.

4. The three-dimensional memory device of claim 3 , wherein each contact area between the discrete annular charge trapping material portions and the insulating layers has an annular shape.

5. The three-dimensional memory device of claim 1 , further comprising:
a first backside blocking dielectric layer contacting the discrete charge trapping material portions and the insulating layers and comprising silicon oxide; and
a second backside blocking dielectric layer contacting the first backside blocking dielectric layer and the electrically conductive layers and comprising a dielectric metal oxide.

6. The three-dimensional memory device of claim 1 , wherein portions of an outer sidewall of the continuous charge trapping material layer located at levels of the electrically conductive layers are vertically coincident with portions of the outer sidewall of the continuous charge trapping material layer located at levels of the insulating layers.

7. The three-dimensional memory device of claim 1 , wherein portions of an outer sidewall of the continuous charge trapping material layer located at levels of the electrically conductive layers protrude outward with respect to portions of the outer sidewall of the continuous charge trapping material layer located at levels of the insulating layers.

8. The three-dimensional memory device of claim 1 , further comprising discrete silicon oxide portions located at levels of the insulating layers, vertically separated from each other, and contacting the outer sidewall of the continuous charge trapping material layer.

9. The three-dimensional memory device of claim 8 , wherein each the discrete silicon oxide portions has an outer sidewall, wherein an upper periphery of the outer sidewall contacts an overlying one of the discrete charge trapping material portions and a lower periphery of the outer sidewall contacts an underlying one of the discrete charge trapping material portions.

10. The three-dimensional memory device of claim 8 , wherein each of the discrete silicon oxide portions comprises:
a vertical portion that extends through a respective one of the insulating layers;
an upper annular horizontal portion that contacts an annular area of a top surface of the respective one of the insulating layers; and
a lower annular horizontal portion that contacts an annular area of a bottom surface of the respective one of the insulating layers.

11. The three-dimensional memory device of claim 1 , wherein:
the alternating stack comprises a terrace region in which each electrically conductive layer other than a topmost electrically conductive layer within the alternating stack laterally extends farther than any overlying electrically conductive layer within the alternating stack;
the terrace region includes stepped surfaces of the alternating stack that continuously extend from a bottommost layer within the alternating stack to a topmost layer within the alternating stack; and
support pillar structures extend through the stepped surfaces and through a retro-stepped dielectric material portion that overlies the stepped surfaces.

12. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

Assignees

• Sandisk Technologies Llc

Inventors

• Zhou Fei
• Makala Raghuveer
• Sharangpani Rahul
• Shukla Keerti
• Zhang Yanli
• Zhang Peng

Classifications

• H01L23/5329

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L21/76898

  Electricity · mapped topic