Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9613979-B2
Application number	US-201615061272-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Jul 16, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Manufactured in a method of manufacturing according to an embodiment is a semiconductor memory device including: control gate electrodes; a semiconductor layer; and a charge accumulation layer. In this method of manufacturing, inter-layer insulating layers and sacrifice layers are stacked alternately, an opening that penetrates the inter-layer insulating layers and sacrifice layers is formed, a first insulating layer, the charge accumulation layer, and the semiconductor layer are formed in the opening, the sacrifice layer and part of the first insulating layer are removed, and the control gate electrodes are formed. An internal diameter of the opening is smaller the more downwardly a portion of the opening is positioned. A film thickness of the first insulating layer is smaller the more downwardly a portion of the first insulating layer is positioned.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of control gate electrodes and a plurality of inter-layer insulating layers stacked alternately above a substrate;
a semiconductor layer having as its longitudinal direction a first direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes;
a charge accumulation layer positioned between the semiconductor layer and the control gate electrode; and
a plurality of first insulating layers separated in the first direction and positioned between the semiconductor layer and the plurality of inter-layer insulating layers, one of the plurality of first insulating layers being a second insulating layer, and another of the plurality of first insulating layers being a third insulating layer positioned above the second insulating layer,
an external diameter of the second insulating layer being smaller than an external diameter of the third insulating layer, and
a film thickness of the second insulating layer being thinner than a film thickness of the third insulating layer.

2. The semiconductor memory device according to claim 1 , wherein
at least one of the plurality of inter-layer insulating layers and at least one of the plurality of first insulating layers are formed from silicon oxide.

3. The semiconductor memory device according to claim 1 , wherein
an impurity contained in at least one of the plurality of inter-layer insulating layers is not included in at least one of the plurality of first insulating layers, or
an impurity contained in at least one of the plurality of first insulating layers is not included in at least one of the plurality of inter-layer insulating layers.

4. The semiconductor memory device according to claim 3 , wherein
at least one of the plurality of inter-layer insulating layers and at least one of the plurality of first insulating layers are configured from silicon oxide (SiO 2 ).

5. The semiconductor memory device according to claim 1 , wherein
an etching rate of at least one of the plurality of inter-layer insulating layers is different from an etching rate of at least one of the plurality of first insulating layers.

6. The semiconductor memory device according to claim 5 , wherein
the etching rates are with respect to hot phosphoric acid or dilute hydrofluoric acid.

Assignees

• Toshiba Kk

Inventors

• Iinuma Toshihiko

Classifications

• H01L21/28282

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title