Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9691783-B2
Application number	US-201414258782-A
Country	US
Kind code	B2
Filing date	Apr 22, 2014
Priority date	Dec 3, 2013
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Provided is a semiconductor device including a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked, a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked, an interfacial pattern formed between the first stacked structure and the second stacked structure, first through-areas passing through the first stacked structure and the interfacial pattern, and including first protrusions protruding toward a sidewall of the interfacial pattern, second through-areas passing through the second stacked structure and connected to the first through-areas, and through-structures formed along sidewalls of the first through-areas and the second through-areas.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked;
a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked;
an interfacial pattern formed between the first stacked structure and the second stacked structure;
first through-areas passing through the first stacked structure and the interfacial pattern and including first protrusions protruding toward a sidewall of the interfacial pattern;
second through-areas passing through the second stacked structure and connected to the first through-areas; and
through-structures formed along sidewalls of the first through-areas and the second through-areas,
wherein the first protrusions define depressions on sidewalls of the first through-areas, the depressions more protruding toward a lateral direction than entire sidewalls of the second through-areas,
wherein the through-structures are formed such that the first conductive patterns and the first interlayer insulating layers between a lowermost layer and an uppermost layer of the first stacked structure have the same structure as the second conductive patterns and the second interlayer insulating layers between a lowermost layer and an uppermost layer of the second stacked structures,
wherein each of the first protrusions and the depressions has a top surface in direct contact with the lowermost layer of the second stacked structure and a bottom surface in direct contact with the uppermost layer of the first stacked structure,
wherein the interfacial pattern is formed of a conductive material, or is formed of an insulating material having an etch selectivity different from etch selectivities of the first and second conductive patterns and the first and second interlayer insulating layers; and
wherein at least one conductive pattern from an uppermost layer among the second conductive patterns is a drain select line, and at least one conductive pattern from a lowermost layer among the first conductive patterns is a source select line.

2. The semiconductor device of claim 1 , wherein each of the through-structures includes a channel layer.

3. The semiconductor device of claim 2 , further comprising:
a bit line connected to an upper part of the channel layer; and
a source area connected to a lower part of the channel layer.

4. The semiconductor device of claim 2 , wherein each of the through-structures further includes a tunnel insulating layer surrounding the channel layer, a data storage layer surrounding the tunnel insulating layer, and a blocking insulating layer surrounding the data storage layer.

5. The semiconductor device of claim 1 , further comprising a slit passing through the first stacked structure, the second stacked structure and the interfacial pattern,
wherein the slit is interposed between adjacent first through-areas and between adjacent second through-areas corresponding to the adjacent first through-areas.

6. The semiconductor device of claim 1 , wherein the interfacial pattern is formed thicker than a conductive pattern adjacent to the interfacial pattern among the first conductive patterns.

7. The semiconductor device of claim 1 , wherein the lowermost layer of the second stacked structure is a protection layer and is in direct contact with the interfacial pattern.

8. The semiconductor device of claim 7 , wherein the first through-area further passes through the protection layer.

9. The semiconductor device of claim 7 , wherein the protection layer is formed of the same material layer as the first interlayer insulating layers.

10. The semiconductor device of claim 1 , wherein the through-structures are in direct contact with sidewalls of the second conductive patterns and sidewalls of the second interlayer insulating layers.

11. A semiconductor device, comprising:
a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked in a first direction;
a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked in the first direction;
an interfacial pattern formed between the first stacked structure and the second stacked structure;
first through-areas passing through the first stacked structure and the interfacial pattern;
first protrusions protruding toward sidewalls of the interfacial pattern from the first through-areas; and
second through-areas passing through the second stacked structure and connected to the first through-areas,
wherein sidewalls of the first protrusions measured from the sidewalls of the interfacial pattern more protrude toward a lateral direction than sidewalls of the second through-areas measured from sidewalls of the second conductive patterns and sidewalls of the second interlayer insulating layers,
wherein each of the first protrusions has a top surface facing a top surface of the first stacked structure in the first direction, and a bottom surface facing a bottom surface of the second stacked structure in the first direction,
wherein the interfacial pattern is formed of a conductive material, or is formed of an insulating material having an etch selectivity different from etch selectivities of the first and second conductive patterns and the first and second interlayer insulating layers; and
wherein at least one conductive pattern from an uppermost layer among the second conductive patterns is a drain select line, and at least one conductive pattern from a lowermost layer among the first conductive patterns is a source select line.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Myung Sung

Classifications

• H01L29/66833

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic