Semiconductor memory device with charge-diffusion-less transistors

Patent metadata

Field	Value
Publication number	US-10032935-B2
Application number	US-201615280013-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Mar 16, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate;
a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate; and
a pillar extending through the multi-layered structure, the pillar including
a semiconductor body extending along the pillar,
a tunnel insulating film provided between the multi-layered structure and the semiconductor body,
a block insulating film provided between the multi-layered structure and the tunnel insulating film, and
a charge-storing film between the tunnel insulating film and the block insulating film, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

2. The semiconductor memory device according to claim 1 , wherein
the charge-storing film has a stacked structure of a first-composition film and a second-composition film, the second-composition film having a larger electric charge trap level than the first-composition film.

3. The semiconductor memory device according to claim 2 , wherein
the first-composition film includes silicon nitride that is more silicon-rich than the second-composition film, which includes silicon nitride or silicon oxynitride.

4. The semiconductor memory device according to claim 2 ,
wherein the second-composition film is between the conductive layer and the tunnel insulating film.

5. The semiconductor memory device according to claim 4 , wherein the first-composition film is in direct contact with the tunnel insulating film at the first portions of the charge-storing film.

6. The semiconductor memory device according to claim 4 , wherein the first-composition film continuously extends through the multi-layered structure and the second-composition film does not continuously extend through the multi-layered structure.

7. The semiconductor memory device according to claim 1 , wherein the block insulating film is in contact with the first-composition film but not in contact with the second-composition film.

8. The semiconductor memory device according to claim 1 , wherein a center portion of each of the insulating portions in a thickness direction thereof protrudes towards the semiconductor body.

9. The semiconductor memory device according to claim 1 , wherein the second portions of the charge-storing film having the second thickness each face one of the conductive layers and extend along an extension direction of the pillar, and a length of each second portion in the extension direction is greater than a thickness of the corresponding conductive layer in the extension direction.

10. The semiconductor memory device according to claim 9 , wherein the first portions of the charge-storing film having the first thickness each face one of the insulating layers and extend along the extension direction, and a length of each first portion in the extension direction is less than a thickness of the corresponding insulating layer in the extension direction.

11. The semiconductor memory device according to claim 10 , wherein the charge-storing film has third portions between the first and second portions in the extension direction, the third portions having a varying thickness between the first thickness and the second thickness.

12. The semiconductor memory device according to claim 1 , wherein an area of a cross-section of the pillar increases as the distance of the cross-section becomes farther from the substrate.

13. A semiconductor memory device comprising:
a substrate;
a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate; and
a pillar extending through the multi-layered structure, the pillar including
a semiconductor body extending along the pillar,
a tunnel insulating film provided between the multi-layered structure and the semiconductor body,
a block insulating film provided between the multi-layered structure and the tunnel insulating film, and
a charge-storing film between the tunnel insulating film and the block insulating film, the charge-storing film having a first thickness at a first portion, a second thickness that is greater than the first thickness at a second portion, and variable thickness between the first and second thicknesses at a third portion between the first portion and the second portion.

14. The semiconductor memory device according to claim 13 , wherein the first portion faces one of the insulating layers, and the second portion faces one of the conductive layers.

15. The semiconductor memory device according to claim 14 , wherein the first portion, the third portion, and the second portion form one continuous portion of the charge-storing film.

16. The semiconductor memory device according to claim 15 , wherein the insulating layer facing the first portion protrudes towards the semiconductor body.

17. The semiconductor memory device according to claim 13 , wherein
the charge-storing film has a stacked structure of a first-composition film and a second-composition film, the second-composition film having a larger electric charge trap level than the first-composition film.

18. The semiconductor memory device according to claim 17 , wherein
the first-composition film includes silicon nitride that is more silicon-rich than the second-composition film, which includes silicon nitride or silicon oxynitride.

19. The semiconductor memory device according to claim 13 , wherein an area of a cross-section of the pillar increases as the distance of the cross-section becomes farther from the substrate.

Assignees

• Toshiba Memory Corp

Inventors

• Higuchi Masaaki
• Shingu Masao
• Kato Tatsuya
• Murata Takeshi
• Fujiwara Makoto
• Kondo Masaki
• Tsuda Muneyuki
• Kurusu Takashi

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title