Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9576977-B2
Application number	US-201614989346-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	May 13, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure including interlayer insulating layers and sacrificial layers that are stacked alternately and penetrated by a hole, wherein the sacrificial layers include first oxidized regions surrounding the hole and non-oxidized regions surrounding the first oxidized regions, wherein the sacrificial layers extend farther toward the hole than the interlayer insulating layers;
forming a base layer along a sidewall of the hole, wherein the base layer includes protrusions formed over the interlayer insulating layers and depressions formed over the sacrificial layers;
removing the non-oxidized regions of the sacrificial layers to expose the first oxidized regions of the sacrificial layers;
partially etching the first oxidized regions of the sacrificial layers to expose edges of the protrusions of the base layer;
forming second oxidized regions by oxidizing the edges of the protrusions of the base layer to a predetermined thickness;
exposing the depressions of the base layer and the edges of the protrusions of the base layer by removing the second oxidized regions of the base layer and the first oxidized regions of the sacrificial layers; and
forming blocking insulation patterns by oxidizing the edges of the protrusions of the base layer and the depressions of the base layer.

2. The method of claim 1 , wherein the forming of the stacked structure comprises:
alternately stacking the interlayer insulating layers and the sacrificial layers;
forming the hole extending through the interlayer insulating layers and the sacrificial layers;
etching portions of the interlayer insulating layers exposed by the hole to form openings through which sidewalls of the sacrificial layers are exposed by a predetermined thickness; and
forming the first oxidized regions by oxidizing the exposed sidewalls of the sacrificial layers.

3. The method of claim 1 , further comprising, before the removing of the non-oxidized regions of the sacrificial layers:
forming a tunnel insulating layer over a surface of the base layer; and
forming a channel layer over the tunnel insulating layer by filling the hole.

4. The method of claim 3 , wherein the forming of the blocking insulating patterns is performed until the blocking insulation patterns contact the tunnel insulating layer at edges of the protrusions of the base layer.

5. The method of claim 1 , wherein the removing of the non-oxidized regions of the sacrificial layers includes forming a slit extending through the stacked structure to expose the non-oxidized regions.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Deung Kak

Classifications

• H10P50/283

  by chemical means · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L27/1158

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic