Selective source/drain recess for improved performance, isolation, and scaling

Patent metadata

Field	Value
Publication number	US-11205723-B2
Application number	US-201916454561-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 27, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin over a substrate;
forming a source or drain (S/D) region on a surface of the substrate, the S/D region positioned between the semiconductor fin and the substrate;
forming a liner over a surface of the semiconductor fin;
recessing a top surface of the substrate to expose a sidewall of the S/D region;
forming a mask over the semiconductor fin and the liner, the mask patterned to expose a top surface and a sidewall of the liner;
recessing a sidewall of the S/D region; and
forming a shallow trench isolation region on the recessed top surface of the substrate, the shallow trench isolation region adjacent to the recessed sidewall of the S/D region.

2. The method of claim 1 , wherein recessing the sidewall of the S/D region comprises a wet etch selective to the liner.

3. The method of claim 1 , wherein recessing the top surface of the substrate defines a first trench having a first width.

4. The method of claim 3 , wherein recessing the sidewall of the S/D region defines a second trench having a second width greater than the first width.

5. The method of claim 4 , wherein a sidewall of the second trench is coplanar to a sidewall of the semiconductor fin.

6. The method of claim 4 , wherein forming the shallow trench isolation region comprises filling the second trench with a dielectric material.

7. The method of claim 1 , wherein the sidewall of the S/D region is recessed in a direction substantially perpendicular to a major surface of the substrate.

8. The method of claim 1 further comprising recessing a sidewall of the substrate.

9. A method for forming a semiconductor device, the method comprising:
forming a pair of semiconductor fins over a substrate;
forming a liner over a surface of the semiconductor fins;
recessing a top surface of the substrate between the semiconductor fins;
forming a mask over the semiconductor fins and the liner, the mask patterned to expose a top surface and a sidewall of the liner;
recessing a sidewall of the substrate, wherein recessing the sidewall of the substrate comprises a wet etch selective to the liner; and
forming a shallow trench isolation region on the recessed surface of the substrate.

10. The method of claim 9 , wherein recessing the top surface of the substrate defines a first trench having a first width.

11. The method of claim 10 , wherein recessing the sidewall of the substrate defines a second trench having a second width greater than the first width.

12. The method of claim 11 , wherein a sidewall of the second trench is coplanar to a sidewall of the semiconductor fin.

13. The method of claim 11 , wherein forming the shallow trench isolation region comprises filling the second trench with a dielectric material.

14. The method of claim 9 , wherein the sidewall of the substrate is laterally recessed.

15. The method of claim 9 further comprising forming a source or drain (S/D) region on a surface of the substrate, the S/D region positioned between the semiconductor fins and the substrate.

16. The method of claim 15 further comprising recessing a sidewall of the S/D region.

Assignees

• IBM

Inventors

• Rahman Ardasheir
• Anderson Brent
• Wang Junli
• Sieg Stuart
• Waskiewicz Christopher J

Classifications

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D30/027

  of lateral single-gate IGFETs · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title