Active area shapes reducing device size

Patent metadata

Field	Value
Publication number	US-9929236-B1
Application number	US-201715624762-A
Country	US
Kind code	B1
Filing date	Jun 16, 2017
Priority date	Feb 3, 2017
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.

First claim

What is claimed is:

1. A method of forming a transistor structure comprising:
performing a patterning process on a planar surface of a substrate to define an area for a first set of transistors and a second set of transistors adjacent the first set of transistors, the patterning process positions a first transistor and a second transistor in the area for the first set of transistors, and a third transistor and a fourth transistor in the area for the second set of transistors;
adding impurities to the area for the first set of transistors to provide the first transistor with an opposite polarity from the second transistor; and
adding impurities to the area for the second set of transistors to provide the third transistor with an opposite polarity from the fourth transistor,
the patterning process patterns an active area of the first transistor to have a four-sided rectangular shape along the planar surface, so that one side of the active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight,
the patterning process patterns an active area of the fourth transistor to have a four-sided rectangular shape along the planar surface, so that one side of the active area of the fourth transistor contacts an active area of the third transistor along a second common edge that is straight and parallel to the first common edge,
the patterning process patterns the active area of the second transistor to lie along the planar surface and to have a third edge, opposite the first common edge, that has a non-linear shape,
the patterning process patterns the active area of the third transistor to lie along the planar surface and to have a fourth edge, opposite the second common edge, that has a shape that is the same as the non-linear shape,
the patterning process patterns the non-linear shape of the third edge to face the non-linear shape of the fourth edge along the planar surface, and
the patterning process patterns the non-linear shape of the third edge to be inverted relative to the non-linear shape of the fourth edge along the planar surface.

2. The method according to claim 1 , the patterning process patterns the non-linear shape to have two sections parallel to the first common edge and the second common edge, and a third section perpendicular to the two sections that connects the two sections.

3. The method according to claim 1 , the patterning process patterns the third edge to be separated from the fourth edge only by an insulator.

4. The method according to claim 1 , the processes of adding the impurities to the area for the first set of transistors and the second set of transistors:
dopes the first transistor and the fourth transistor to have the same first doping impurities and the same first polarity, and
dopes the second transistor and the third transistor to have the same second doping impurities and the same second polarity,
the first doping impurities are different from the second doping impurities.

5. The method according to claim 1 , the patterning process patterns the first common edge to be shared by the active area of the first transistor and the active area of the second transistor and to define a border between the active area of the first transistor and the active area of the second transistor, and
the patterning process patterns the second common edge to be shared by the active area of the third transistor and the active area of the fourth transistor and to define a border between the active area of the third transistor and the active area of the fourth transistor.

6. The method according to claim 1 , the patterning process patterns the active area of the second transistor and the active area of the third transistor to be between the active area of the first transistor and the active area of the fourth transistor along the planar surface.

7. The method according to claim 1 , the patterning process patterns the active area of the first transistor and the active area of the fourth transistor to have the same four-sided rectangular shape and size,
the patterning process patterns the active area of the second transistor and the active area of the third transistor to have the same six-sided shape and size, and
the patterning process patterns the shape of the active area of the third transistor to be inverted relative to the shape of the active area of the second transistor.

8. A method of forming a transistor structure comprising:
patterning a substrate to form fins on a planar surface of the substrate;
performing a patterning process on the planar surface of the substrate to define an area for a first set of transistors and a second set of transistors adjacent the first set of transistors, the patterning process positions fins of a first transistor and a second transistor in the area for the first set of transistors, and fins of a third transistor and a fourth transistor in the area for the second set of transistors;
adding impurities to the area for the first set of transistors adjacent the fins to provide the first transistor with an opposite polarity from the second transistor; and
adding impurities to the area for the second set of transistors adjacent the fins to provide the third transistor with an opposite polarity from the fourth transistor,
the patterning process patterns an active area of the first transistor to have a four-sided rectangular shape along the planar surface, so that one side of the active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight,
the patterning process patterns an active area of the fourth transistor to have a four-sided rectangular shape along the planar surface, so that one side of the active area of the fourth transistor contacts an active area of the third transistor along a second common edge that is straight and parallel to the first common edge,
the patterning process patterns the active area of the second transistor to lie along the planar surface and to have a third edge, opposite the first common edge, that has a non-linear shape,
the patterning process patterns the active area of the third transistor to lie along the planar surface and to have a fourth edge, opposite the second common edge, that has a shape that is the same as the non-linear shape,
the patterning process patterns the non-linear shape of the third edge to face the non-linear shape of the fourth edge along the planar surface, and
the patterning process patterns the non-linear shape of the third edge to be inverted relative to the non-linear shape of the fourth edge along the planar surface.

9. The method according to claim 8 , the patterning process patterns the non-linear shape to have two sections parallel to the first common edge and the second common edge, and a third section perpendicular to the two sections that connects the two sections.

10. The method according to claim 8 , the patterning process patterns the third edge to be separated from the fourth edge only by an insulator.

11. The method according to claim 8 , the processes of adding impurities to the area for the first set of transistors and the second set of transistors:
dopes the first transistor and the fourth transistor to have the same first doping impurities and the same first polarity, and
dopes the second transistor and the third transistor to have the same second doping impurities and the same second polarity,
the first doping impurities are different from the second doping impurities.

12. The method according to claim 8 , the patterning process patterns the first common edge to be shared by the active area of the first transisto

Assignees

• Globalfoundries Inc

Inventors

• Paul Bipul C
• Lim Kwan-Yong

Classifications

• H01L29/0692 Primary

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L27/1108

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic