Vertical transistors with merged active area regions

Patent metadata

Field	Value
Publication number	US-9761712-B1
Application number	US-201615338867-A
Country	US
Kind code	B1
Filing date	Oct 31, 2016
Priority date	Oct 31, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.

First claim

What is claimed is:

1. A method for device layout with vertical transistors, comprising:
identifying active area regions in a layout of a semiconductor device with vertical transistors;
determining sets of adjacent active area regions having a same electrical potential;
prioritizing the sets of adjacent active area regions to be merged based upon one or more performance criterion, wherein the one or more performance criterion is selected from the group consisting of resistance, capacitance, variability reduction, thermal resistance, circuit performance and reduction of worst case variability; and
merging the sets of adjacent active area regions to form larger active area regions according to a priority set by setting rules to determine when and how merging is performed.

2. The method as recited in claim 1 , further comprising:
identifying fill or no fill regions adjacent to active area regions in the layout;
merging the fill or no fill regions with the sets of adjacent active area regions to form larger active area regions.

3. The method as recited in claim 2 , wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a fixed or transient potential next to a fill or no fill region.

4. The method as recited in claim 1 , wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a same fixed potential.

5. The method as recited in claim 1 , wherein merging the sets of adjacent active area regions includes modifying shapes of the active area regions to merge prioritized active area regions.

6. The method as recited in claim 1 , wherein merging the sets of adjacent active area regions includes merging active area regions between logic devices.

7. The method as recited in claim 6 , wherein the logic devices are selected from the group consisting of combinatorial logic elements and sequential logic elements.

8. The method as recited in claim 1 , further comprising connecting the larger active area regions to one or more continuous buses where the continuous buses replace a plurality of separate supply or ground contacts.

9. The method as recited in claim 1 , wherein merging the sets of adjacent active area regions further comprises reducing trench isolation regions between the sets of adjacent active area regions.

10. The method as recited in claim 1 , wherein merging the sets of adjacent active area regions includes merging the sets of adjacent active area regions across cell boundaries.

11. A non-transitory computer readable storage medium comprising a computer readable program for device layout with vertical transistors, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
identifying active area regions in a layout of a semiconductor device with vertical transistors;
determining sets of adjacent active area regions having a same electrical potential;
prioritizing the sets of adjacent active area regions to be merged based upon one or more performance criterion, wherein the one or more performance criterion is selected from the group consisting of resistance, capacitance, variability reduction, thermal resistance, circuit performance and reduction of worst case variability; and
merging the sets of adjacent active area regions to form larger active area regions according to a priority set by setting rules to determine when and how merging is performed.

12. The computer readable storage medium as recited in claim 11 , further comprising:
identifying fill or no fill regions adjacent to active area regions in the layout;
merging the fill or no fill regions with the sets of adjacent active area regions to form larger active area regions.

13. The computer readable storage medium as recited in claim 12 , wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a fixed or transient potential next to a fill or no fill region.

14. The computer readable storage medium as recited in claim 11 , wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a same fixed potential.

15. The computer readable storage medium as recited in claim 11 , wherein merging the sets of adjacent active area regions includes merging active area regions between logic devices selected from the group consisting of combinatorial logic elements and sequential logic elements.

16. The computer readable storage medium as recited in claim 11 , further comprising:
connecting the larger active area regions to one or more continuous buses where the continuous busses replace a plurality of separate supply or ground contacts; and
reducing trench isolation regions between the sets of adjacent active area regions.

17. The computer readable storage medium as recited in claim 11 , wherein merging the sets of adjacent active area regions includes merging the sets of adjacent active area regions across cell boundaries.

18. A method for device layout with vertical transistors, comprising:
identifying active area regions in a layout of a semiconductor device with vertical transistors;
determining sets of adjacent active area regions having a same electrical potential;
prioritizing the sets of adjacent active area regions to be merged based upon one or more performance criterion;
merging the sets of adjacent active area regions to form larger active area regions according to a priority set by setting rules to determine when and how merging is performed; and
connecting the larger active area regions to one or more continuous buses where the continuous buses replace a plurality of separate supply or ground contacts.

19. The method as recited in claim 18 , further comprising:
identifying fill or no fill regions adjacent to active area regions in the layout;
merging the fill or no fill regions with the sets of adjacent active area regions to form larger active area regions, wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a fixed or transient potential next to a fill or no fill region.

20. The method as recited in claim 18 , wherein determining the sets of adjacent active area regions having the same electrical potential includes determining the sets of adjacent active area regions having a same fixed potential.

21. The method as recited in claim 18 , wherein the one or more performance criterion is selected from the group consisting of resistance, capacitance, variability reduction, thermal resistance, circuit performance and reduction of worst case variability.

22. The method as recited in claim 18 , wherein merging the sets of adjacent active area regions includes modifying shapes of the active area regions to merge prioritized active area regions.

23. The method as recited in claim 18 , wherein merging the sets of adjacent active area regions includes merging active area regions between logic devices, wherein the logic devices are selected from the group consisting of combinatorial logic elements and sequential logic elements.

Assignees

• IBM

Inventors

• Anderson Brent A
• Chu Albert M
• Hook Terence B
• Kim Seong-Dong

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/427

  Power or ground buses · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2111/06

  Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA] · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title