Vertical field effect transistors

Patent metadata

Field	Value
Publication number	US-9570357-B2
Application number	US-201514965988-A
Country	US
Kind code	B2
Filing date	Dec 11, 2015
Priority date	Dec 4, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.

First claim

What is claimed:

1. A method, comprising:
forming at least one vertical fin structure;
forming gate material contacting with the at least one vertical fin structure; and
forming source and drain contacts at ends of the at least one vertical fin structure by deposition of metal material in electrical contact with the silicide regions, wherein
the at least one vertical fin structure comprises at least two adjacent vertical fin structures; and
the forming of the gate material includes depositing a gate dielectric material and a metal material on the at least two adjacent vertical fin structures, and patterning the gate dielectric material and the metal material to form a space between the at least two adjacent vertical fin structures.

2. The method of claim 1 , wherein the forming of the at least one vertical fin structure comprises:
patterning a first portion of the at least one vertical fin structure from semiconductor material, the first portion having a first dimension;
patterning a second portion of the at least one vertical fin structure from the semiconductor material with a second dimension narrower than the first dimension; and
epitaxially growing semiconductor material on the second portion to form a third portion with a third dimension wider than the second dimension.

3. The method of claim 1 , further comprising forming an air gap by depositing an interlevel dielectric between the least two adjacent vertical fin structures.

4. The method of claim 1 , wherein at least one of a drain region and a source region of the least two adjacent vertical fin structures are merged together during patterning of the least two adjacent vertical fin structures.

5. The method of claim 1 , wherein at least one of drain region and source region of the least two adjacent vertical fin structures are connected together by forming a conductive strap.

6. The method of claim 1 , further comprising forming a low resistance conductor layer at a bottom portion of the at least one vertical fin structure.

7. The method of claim 1 , wherein the gate material is formed entirely around a vertical extent of the at least one vertical fin structure.

8. The method of claim 1 , wherein the gate material is formed on a single side of a vertical extent of the at least one vertical fin structure.

9. The method of claim 2 , wherein the forming of the source and drain contacts comprises subjecting the first portion and third portion to a silicide process followed by the deposition of the metal material in an opening of a dielectric material.

10. A method comprising:
forming at least two adjacent fin structures with a source region and a drain region at opposing ends, from semiconductor material formed on a dielectric material;
forming gate material about the two adjacent fin structures and between the opposing ends by depositing the gate material following by a patterning of the gate material to form a space between the gate material of the two adjacent fin structures; and
forming drain contacts and source contacts at the opposing ends of the two adjacent fin structures on the source region and the drain region.

11. The method of claim 10 , wherein:
the forming of the source region and drain region of the at least two adjacent fin structures comprises patterning semiconductor material to a first dimension and epitaxially growing semiconductor material on a narrow portion above the first dimension; and
the forming of the drain contacts and the source contacts comprises subjecting the source region and drain region of each of the at least two adjacent fin structures to a silicide process followed by deposition of metal material in an opening of a dielectric material.

12. The method of claim 10 , further comprising forming a low resistance conductor layer at a bottom portion of the least two adjacent vertical fin structures.

13. The method of claim 11 , wherein the forming of the gate material includes depositing a gate dielectric material and a metal material on the narrow portion of the at least two adjacent vertical fin structures, and patterning the gate dielectric material and the metal material to form a space therebetween.

14. The method of claim 11 , further comprising forming an air gap by depositing an interlevel dielectric between the least two adjacent vertical fin structures.

15. The method of claim 11 , wherein at least one of the drain region and the source region of the least two adjacent vertical fin structures are merged together during patterning of the least two adjacent vertical fin structures.

16. The method of claim 11 , wherein at least one of the drain region and the source region of the least two adjacent vertical fin structures are connected together by forming a conductive strap.

17. The method of claim 11 , wherein the gate material is formed entirely around a vertical extent of the at least one vertical fin structure.

18. The method of claim 11 , wherein the gate material is formed on a single side of a vertical extent of the at least one vertical fin structure.

Assignees

• IBM

Inventors

• Anderson Brent A
• Nowak Edward J

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W10/021

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic