Vector operands with component representing different significance portions

Patent metadata

Field	Value
Publication number	US-9766858-B2
Application number	US-201414582968-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.

First claim

We claim:

1. Apparatus for processing data comprising:
a vector storage element to store a vector of input operand data, said vector having one or more components representing respective different bit significance portions of the same binary number;
a metadata storage element to store metadata representing at least how many of said one or more components are within said vector;
where programmable significance data specifies a bit significance of said binary number; and
processing circuitry to perform a processing operation upon said vector in dependence upon both a program instruction and said metadata, said processing circuitry including at least one of: one or more integer adders and one or more integer multipliers.

2. Apparatus as claimed in claim 1 , wherein said metadata specifies a bit length of said one or more components.

3. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises micro-operation generating circuitry to generate one or more micro-operation instructions for controlling said processing circuitry to perform said processing operation specified by said program instruction, said one or more micro-operation instructions generated being dependent said metadata and matched to available hardware resources of said processing circuitry.

4. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises a plurality of arithmetic circuits with a bit width less than said vector and said metadata controls carry propagation between said plurality of arithmetic circuits operating in parallel.

5. Apparatus as claimed in claim 1 , wherein said processing circuitry comprises one or more arithmetic circuits with a bit width less than said vector and said metadata controls carry propagation between said one or more arithmetic circuits operating in series.

6. Apparatus as claimed in claim 1 , wherein said programmable significance data is indicative of range of bit significance corresponding to said vector, said range being a proper subset of a full range of bit significance.

7. Apparatus as claimed in claim 6 , wherein said apparatus supports floating point processing operations performed using floating point operands and said full range of bit significance corresponds to a range of bit significance representable using said floating point operands.

8. Apparatus for processing data comprising:
vector storage means for storing a vector of input operand data, said vector having one or more components representing respective different bit significance portions of the same binary number;
metadata storage means for storing metadata representing at least how many of said one or more components are within said vector;
where programmable significance data specifies a bit significance of said binary number; and
processing means for performing a processing operation upon said vector in dependence upon both a program instruction and said metadata, said processing means including at least one of: one or more means for integer adding and one or more means for integer multiplying.

9. A method of processing data comprising:
storing a vector of input operand data, said vector having one or more components representing respective different bit significance portions of the same binary number;
storing metadata representing at least how many of said one or more components are within said vector;
storing programmable significance data specifying a bit significance of said binary number; and
performing a processing operation upon said vector in dependence upon both a program instruction and said metadata, wherein said processing operation is performed using processing circuitry including at least one of: one or more integer adders and one or more integer multipliers.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil
• Hinds Christopher Neal

Classifications

• G06F11/3636 Primary

  by tracing the execution of the program · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title

• H03M7/12

  having two radices, e.g. binary-coded-decimal code · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title