Arithmetic circuit and arithmetic method

Patent metadata

Field	Value
Publication number	US-9632751-B2
Application number	US-201314140384-A
Country	US
Kind code	B2
Filing date	Dec 24, 2013
Priority date	Dec 26, 2012
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value.

First claim

What is claimed is:

1. An arithmetic circuit comprising:
an arithmetic unit configured to perform processing comprising an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits, where n is an integer of not less than 1 and m is an integer of not less than 2;
a rounding preprocessor configured to perform processing comprising compressing lower (m−1) bits of the first value generated by the arithmetic unit by performing an OR operation on the lower (m−1) bits of the first value to generate a second value of 1 bit;
a register which stores a third value of (n+2) bits obtained by concatenating upper (n+1) bits of the first value and the second value; and
a rounding postprocessor configured to determine an addition value of 2 bit based on a most significant bit of the third value, add the addition value to the third value to generate a fourth value, and remove lower two bits of the fourth value,
wherein at least a part of the processing of the rounding preprocessor is performed in parallel with a part of the processing of the arithmetic unit.

Assignees

• Toshiba Kk

Inventors

• Ban Koichiro

Classifications

• G06F7/49952

  Sticky bit · CPC title

• G06F7/5312

  using carry save adders · CPC title

• G06F7/49963 Primary

  Rounding to nearest (G06F7/49957 takes precedence) · CPC title

• G06F7/506

  with simultaneous carry generation for, or propagation over, two or more stages · CPC title