Compaction of multiplier and adder circuits
US-11768663-B1 · Sep 26, 2023 · US
with simultaneous carry generation for, or propagation over, two or more stages
with simultaneous carry generation for, or propagation over, two or more stages · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/506 |
| Official title | with simultaneous carry generation for, or propagation over, two or more stages |
| Display label | with simultaneous carry generation for, or propagation over, two or more stages |
| Total patents | 67 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is growing.
| Year | Patents |
|---|---|
| 2015 | 3 |
| 2016 | 13 |
| 2017 | 8 |
| 2018 | 7 |
| 2019 | 5 |
| 2020 | 11 |
| 2021 | 4 |
| 2022 | 4 |
| 2023 | 6 |
| 2024 | 1 |
| 2025 | 5 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Pipelines for power and area savings and for higher parallelism
US-2023259330-A1 · Aug 17, 2023 · US
Using and/or reduce carry chains on programmable hardware
US-2023214180-A1 · Jul 6, 2023 · US
Adder circuitry for very large integers
US-11662979-B2 · May 30, 2023 · US
In-memory full adder
US-11604850-B2 · Mar 14, 2023 · US
Large integer multiplication enhancements for graphics environment
US-2022413848-A1 · Dec 29, 2022 · US
Computing array based on 1T1R device, operation circuits and operating methods thereof
US-11475949-B2 · Oct 18, 2022 · US
New low power adder tree structure
US-2022253282-A1 · Aug 11, 2022 · US
Prefix network-directed addition
US-11334318-B2 · May 17, 2022 · US
Computing array based on 1t1r device, operation circuits and operating methods thereof
US-2021327505-A1 · Oct 21, 2021 · US
Parallel-prefix adder and method
US-11010133-B2 · May 18, 2021 · US
Adder circuitry for very large integers
US-2021075425-A1 · Mar 11, 2021 · US
FPGA logic cell with improved support for counters
US-10936286-B2 · Mar 2, 2021 · US
Adder circuitry for very large integers
US-10873332-B2 · Dec 22, 2020 · US
Parallel-prefix adder and method
US-2020334014-A1 · Oct 22, 2020 · US
Arithmetic logic unit for single-cycle fusion operations
US-10768897-B2 · Sep 8, 2020 · US
High spurious-free dynamic-range line driver
US-10715147-B1 · Jul 14, 2020 · US
Parallel-prefix adder and method
US-10705797-B2 · Jul 7, 2020 · US
Parallel-prefix adder and method
US-2020167127-A1 · May 28, 2020 · US
Fpga logic cell with improved support for counters
US-2020150925-A1 · May 14, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/506?
- CPC G06F7/506 is the Cooperative Patent Classification code for “with simultaneous carry generation for, or propagation over, two or more stages.”
- How many patents are filed under CPC G06F7/506 (with simultaneous carry generation for, or propagation over, two or more stages)?
- Our database includes 67 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/506 growing?
- Publication counts under this code: 1 in 2024 vs 5 in 2025 (latest complete years).