Exception generation when generating a result value with programmable bit significance

Patent metadata

Field	Value
Publication number	US-9703529-B2
Application number	US-201414582978-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.

First claim

We claim:

1. Apparatus for processing data comprising:
processing circuitry to perform a processing operation upon one or more input operands to generate a result value having a programmable bit significance; and
exception generating circuitry to generate one or more exception indications in dependence on the processing operation performed by the processing circuitry, wherein
said one or more exception indications include an overflow exception indicative of at least a portion of a result of said processing operation larger than representable within said result value having said programmable bit significance;
wherein said programmable bit significance is specified by an anchor value having a number of bits sufficient for the result value having said programmable bit significance to be capable of representing a range of bit significance extending at least from a lower boundary of bit significance corresponding to a smallest bit significance that can be represented by a single precision or double precision floating point value up to an upper boundary of bit significance corresponding to a highest bit significance that can be represented by the single precision or double precision floating point value.

2. Apparatus as claimed in claim 1 , wherein said processing operation is a conversion from a floating point input operand to an anchored result with said programmable bit significance.

3. Apparatus as claimed in claim 1 , wherein said processing operation is an arithmetic operation performed upon one or more floating point input operands to generate an anchored result value with said programmable bit significance.

4. Apparatus as claimed in claim 1 , wherein said processing operation is an arithmetic operation performed upon one or more anchored input operands to generate an anchored result value with said programmable bit significance.

5. Apparatus as claimed in claim 4 , wherein said one or more anchored input operands have said programmable bit significance.

6. Apparatus as claimed in claim 1 , wherein said one or more exception indications include an underflow exception indicative of at least a portion of said a result of said processing operation smaller than representable within said result value having said programmable bit significance.

7. Apparatus as claimed in claim 1 , wherein said one or more exception indications include an inexact exception indicative of a result of said processing operation inexactly represented by said result value having said programmable bit significance.

8. Apparatus as claimed in claim 1 , wherein said one or more exception indications include an invalid operation exception indicative of said processing operation being an invalid processing operation.

9. Apparatus as claimed in claim 1 , wherein at least one of said input operand is a floating point input operand and said one or more exception indications include an input subnormal exception indicative of said floating point input operand being a subnormal floating point input operand.

10. Apparatus as claimed in claim 1 comprising one or more metadata storage elements to store metadata for a subject value that is one of said one or more input operands and said result value and indicating if said subject is of at least one of an infinity value, a not-a-number value and a signed value.

11. Apparatus as claimed in claim 1 , wherein said processing circuitry is configured to perform a further processing operation upon one or more input anchored operands having a programmable bit significance to generate a floating point result value.

12. Apparatus as claimed in claim 11 , wherein said further processing operation is a conversion from an anchored input operand to a floating point result.

13. Apparatus as claimed in claim 11 , wherein said further processing operation is an arithmetic operation performed upon one or more anchored input operands to generate a floating point result value.

14. Apparatus as claimed in claim 1 , comprising a global exception storage element to store data indicative of an exception arising during operation of said apparatus.

15. Apparatus as claimed in claim 1 , wherein said result value is a vector comprising a plurality of components having respective component bit significance ranges that together correspond to said programmable bit significance.

16. Apparatus as claimed in claim 1 , comprising a result register to store said result value, wherein said programmable bit significance is specified for said result register and said result value is aligned to match said programmable bit significance of said result register.

17. Apparatus as claimed in claim 16 , wherein said programmable bit significance is metadata specified for said result register.

18. Apparatus as claimed in claim 1 , wherein said processing operation is specified by a program instruction and said program instruction is independent of said programmable bit significance.

19. Apparatus for processing data comprising:
means for performing a processing operation upon one or more input operands to generate a result value having a programmable bit significance; and
means for generating one or more exception indications in dependence on the processing operation performed by the means for performing, wherein
said one or more exception indications include an overflow exception indicative of at least a portion of a result of said processing operation larger than representable within said result value having said programmable bit significance;
wherein said programmable bit significance is specified by an anchor value having a number of bits sufficient for the result value having said programmable bit significance to be capable of representing a range of bit significance extending at least from a lower boundary of bit significance corresponding to a smallest bit significance that can be represented by a single precision or double precision floating point value up to an upper boundary of bit significance corresponding to a highest bit significance that can be represented by the single precision or double precision floating point value.

20. A method of processing data comprising:
specifying a programmable bit significance of a result value;
performing a processing operation upon one or more input operands to generate said result value having said programmable bit significance; and
generating one or more exception indications in dependence on the processing operation performed upon the one or more input operands, wherein
said one or more exception indications include an overflow exception indicative of at least a portion of a result of said processing operation larger than representable within said result value having said programmable bit significance;
wherein said programmable bit significance is specified by an anchor value having a number of bits sufficient for the result value having said programmable bit significance to be capable of representing a range of bit significance extending at least from a lower boundary of bit significance corresponding to a smallest bit significance that can be represented by a single precision or double precision floating point value up to an upper boundary of bit significance corresponding to a highest bit significance that can be represented by the single precision or double precision floating point value.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil
• Hinds Christopher Neal

Classifications

• G06F2207/483

  Indexing scheme relating to group G06F7/483 · CPC title

• G06F7/38

  Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title