Apparatus and method for performing conversion operation

Patent metadata

Field	Value
Publication number	US-9665347-B2
Application number	US-201414582812-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

First claim

We claim:

1. An apparatus comprising:
processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a floating-point value comprising an alternative representation of said binary value; the processing circuitry comprising:
exponent determining circuitry to determine an exponent of the floating-point value based on a position of a most significant non-sign bit within the plurality of data elements and a significance of the data element comprising the most significant non-sign bit; and
significand determining circuitry to perform a significand generation operation to generate a partial significand value for at least one of the plurality of data elements, and to form a significand of the floating-point value based on the partial significand value generated for said at least one data element.

2. The apparatus according to claim 1 , wherein the significand generation operation for a selected data element comprises detecting whether the selected data element comprises at least one non-sign bit, and when the selected data element comprises at least one non-sign bit, outputting as the partial significand value for the selected data element a most significant non-sign bit and a number of less significant bits of the data element selected depending on the position of the most significant non-sign bit within the selected data element.

3. The apparatus according to claim 1 , wherein the processing circuitry is configured to perform the significand generation operation in parallel for at least some of the plurality of data elements.

4. The apparatus according to claim 1 , wherein the processing circuitry is configured to perform the significand generation operation sequentially for at least some of the plurality of data elements.

5. The apparatus according to claim 4 , wherein the significand generation operation for a later processed data element is dependent on information generated in the significand generation operation for an earlier processed data element.

6. The apparatus according to claim 4 , wherein the processing circuitry is configured to perform the significand generation operation for a first data element before performing the significand generation operation for a second data element representing a less significant bit significance portion of the first value than the first data element.

7. The apparatus according to claim 6 , wherein in the significand generation operation for the first data element, when the partial significand value generated for the first data element comprises fewer bits than a number of bits required for a significand of the floating-point value, the processing circuitry is configured to output a control value indicating a number of remaining bits of the significand of the floating-point value to be generated, and
in the significand generation operation for the second data element, the processing circuitry is configured to generate the partial significand value comprising a number of bits of the second data element selected based on the control value output for the first data element.

8. The apparatus according to claim 4 , wherein the processing circuitry is configured to perform the significand generation operation for a first data element before performing the significand generation operation for a second data element representing a more significant portion of the first value than the first data element.

9. The apparatus according to claim 1 , wherein in the conversion operation, the processing circuitry is to generate the floating-point value in dependence on the vector and programmable control information.

10. The apparatus according to claim 9 , wherein the control information is indicative of a significance of the bit significance portions represented by the data elements.

11. The apparatus according to claim 10 , wherein the control information is indicative of a significance of the bit significance portion represented by a predetermined data element of said plurality of data elements, and the processing circuitry is to determine the significance of the bit significance portion to be represented by at least one other data element in dependence on the significance indicated for the predetermined data element.

12. The apparatus according to claim 10 , wherein the control information comprises separate indications of the significance of the bit significance portions represented by the plurality of data elements.

13. The apparatus according to claim 9 , wherein the control information is indicative of a variable number of data elements of the vector.

14. The apparatus according to claim 1 , wherein the vector comprises a greater number of bits than the floating-point value.

15. The apparatus according to claim 1 , wherein the processing circuitry comprises a plurality of processing units to process at least two of the data elements in parallel.

16. The apparatus according to claim 1 , wherein the processing circuitry is configured to determine whether the binary value represented by the vector is negative, and when the binary value is negative, to perform a negation operation during the conversion operation to generate the significand of the floating-point value with a value negated relative to at least part of at least one data element of the vector.

17. The apparatus according to claim 1 , wherein the processing circuitry is to perform the conversion operation in response to a first instruction.

18. The apparatus according to claim 17 , wherein the first instruction comprises a conversion instruction.

19. The apparatus according to claim 17 , wherein the first instruction comprises an arithmetic instruction.

20. A data processing method comprising:
performing, using processing circuitry, a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a floating-point value comprising an alternative representation of said binary value;
determining an exponent of the floating-point value based on a position of a most significant non-sign bit within the plurality of data elements and a significance of the data element comprising the most significant non-sign bit; and
performing a significand generation operation to generate a partial significand value for at least one of the plurality of data elements, and forming a significand of the floating-point value based on the partial significand value generated for said at least one data element.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil
• Hinds Christopher Neal

Classifications

• G06F7/48

  using non-contact-making devices, e.g. tube, solid state device; using unspecified devices · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title

• G06F11/3644

  by instrumenting at runtime · CPC title