Significance alignment

Patent metadata

Field	Value
Publication number	US-9690543-B2
Application number	US-201414582974-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value.

First claim

We claim:

1. Apparatus for processing data comprising:
alignment circuitry to align, with respect to bit significance, any of one or more input operands to a programmable significance parameter specified for an output storage element to provide one or more aligned input operands, wherein the programmable significance parameter is indicative of which powers of 2 are to be represented by respective bits of a result value to be stored in the output storage element, and at least one of said one or more input operands is a floating point input operand having an exponent value and a significand value and said alignment circuitry is responsive to said programmable significance parameter and said exponent value to align, with respect to bit significance, said significand with said result value; and
arithmetic circuitry coupled to said alignment circuitry to receive said one or more aligned input operands, to perform an arithmetic operation upon said one or more aligned input operands to generate said result value, and to store said result value to said output storage element, wherein said arithmetic circuitry comprises an integer adder or an integer multiplier;
wherein said programmable significance parameter is independent of said result value.

2. Apparatus as claimed in claim 1 , wherein at least one of said one or more input operands is an anchored operand with a programmable input operand significance and said alignment circuitry is responsive to said programmable significance parameter and said programmable input operand significance to align, with respect to bit significance, said anchored operand with said result value.

3. Apparatus as claimed in claim 2 , wherein said programmable input operand significance specifies a range between a lower significance boundary and an upper significance boundary.

4. Apparatus as claimed in claim 1 , wherein said programmable significance parameter is set for said output storage element independent of said one or more input operands.

5. Apparatus as claimed in claim 1 , wherein said programmable significance parameter is set for said output storage element to match a highest significance of any of said one or more input operands.

6. Apparatus as claimed in claim 1 , wherein said output storage element is an output register, said programmable significance parameter indicates bit significance of said result value and a programmable length parameter indicates a bit length of said result value.

7. Apparatus for processing data comprising:
first means for aligning, with respect to bit significance, any of one or more input operands to a programmable significance parameter specified for an output storage element to provide one or more aligned input operands, wherein the programmable significance parameter is indicative of which powers of 2 are to be represented by respective bits of a result value to be stored in the output storage element, and at least one of said one or more input operands is a floating point input operand having an exponent value and a significand value and said alignment circuitry is responsive to said programmable significance parameter and said exponent value to align, with respect to bit significance, said significand with said result value; and
second means, coupled to said second means, for receiving said one or more aligned input operands, for performing an arithmetic operation upon said one or more aligned input operands to generate a result value, and for storing said result value to said output storage element, wherein said arithmetic means comprises an integer adder or an integer multiplier;
wherein said programmable significance parameter is independent of said aligned result value.

8. A method of processing data comprising:
aligning, with respect to bit significance, any of one or more input operands to a programmable significance parameter specified for an output storage element to provide one or more aligned input operands, wherein the programmable significance parameter is indicative of which powers of 2 are to be represented by respective bits of a result value to be stored in the output storage element, and at least one of said one or more input operands is a floating point input operand having an exponent value and a significand value, wherein the aligning is responsive to said programmable significance parameter and said exponent value to align, with respect to bit significance, said significand with said result value;
receiving said one or more aligned input operands;
performing an arithmetic operation upon said one or more aligned input operands to generate a result value using arithmetic circuitry comprising an integer adder or an integer multiplier; and
storing said result value to said output storage element,
wherein said programmable significance parameter is independent of said aligned result value.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil
• Hinds Christopher Neal

Classifications

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F7/49942

  Significance control · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title