Data processing apparatus and method using programmable significance data

Patent metadata

Field	Value
Publication number	US-9766857-B2
Application number	US-201414582836-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Nov 3, 2014
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An apparatus includes processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.

First claim

The invention claimed is:

1. An apparatus comprising:
processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand; and
a storage element to store programmable significance data indicative of a target significance for the result value, wherein said target significance is indicative of which powers of 2 are to be represented by respective bits of the result value;
wherein for at least one arithmetic operation, the processing circuitry is responsive to the programmable significance data to generate the result value having the target significance.

2. The apparatus according to claim 1 , the processing circuitry is responsive to the programmable significance data to generate the result value having said target significance independent of a significance of said at least one operand.

3. The apparatus according to claim 1 , wherein the result value comprises a fixed-point data value.

4. The apparatus according to claim 1 , wherein the programmable significance data comprises boundary information indicative of at least one significance boundary for the result value.

5. The apparatus according to claim 4 , wherein the processing circuitry is responsive to the boundary information to determine bit values of the result value having a significance within the at least one significance boundary.

6. The apparatus according to claim 4 , wherein the boundary information comprises at least one of:
lower significance boundary information indicative of a significance of a least significant bit of said result value, and
upper significance boundary information indicative of a significance of a most significant bit of said result value.

7. The apparatus according to claim 1 , wherein the processing circuitry is responsive to programmable size information indicative of a target size for the result value, to generate the result value having the target size.

8. The apparatus according to claim 7 , wherein the processing circuitry comprises hardware to generate up to N bits of the result value in parallel; and
when the programmable size information indicates a target size of more than N bits, the processing circuitry is configured to perform the at least one arithmetic operation in multiple passes of said hardware.

9. The apparatus according to claim 1 , wherein the processing circuitry comprises a plurality of processing units to perform a plurality of parallel lanes of processing;
wherein the programmable significance data specifies, for at least one of the lanes of processing, a target significance for a portion of the result value to be generated by that lane of processing.

10. The apparatus according to claim 9 , wherein each processing unit is configured to form at least one input value based on the at least one operand and the target significance specified for that lane by the programmable significance data, and to process the at least one input value to generate the portion of the result value for that lane of processing.

11. A data processing method comprising:
performing, using processing circuitry, an arithmetic operation to generate a result value based on at least one operand;
storing programmable significance data indicative of a target significance for the result value, wherein said target significance is indicative of which powers of 2 are to be represented by respective bits of the result value;
wherein for at least one arithmetic operation, the processing circuitry is responsive to the programmable significance data to generate the result value having the target significance.

12. An apparatus comprising:
at least one data storage element;
a metadata storage element to store metadata for at least one corresponding data storage element,
wherein the metadata is indicative of a target significance and a target size of a data value to be stored in said at least one corresponding data storage element, and
wherein the target significance is indicative of which powers of 2 are to be represented by respective bits of the data value to be stored in said at least one corresponding data storage element; and
processing circuitry to perform one or more arithmetic operations,
wherein for at least one arithmetic operation for generating the data value to be stored in said at least one corresponding data storage element, the processing circuitry is responsive to the metadata stored in the metadata storage element to generate the data value having the target significance and the target size.

13. The apparatus according to claim 12 , wherein the metadata is programmable.

14. The apparatus according to claim 12 , wherein the metadata storage element comprises part of said at least one corresponding data storage element.

15. The apparatus according to claim 12 , wherein if the target size indicated by the metadata is greater than a data storage element size of said at least one data storage element, then the data value is stored in a plurality of said corresponding data storage elements.

16. The apparatus according to claim 12 , wherein the metadata further comprises at least one of:
exception information indicating whether an exception condition has arisen for the data value stored in said at least one corresponding data storage element;
sign information indicating whether the data value stored in said at least one corresponding data storage element is positive or negative; and
characteristic information indicating a characteristic of the data value stored in said at least one corresponding data storage element.

17. The apparatus according to claim 12 , wherein the metadata comprises exception information, and the processing circuitry is configured to set the exception information to indicate an exception condition if the result of said at least one arithmetic operation is outside a range of values representable by the data value having the target significance and the target size.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lutz David Raymond
• Burgess Neil
• Hinds Christopher Neal

Classifications

• G06F11/348

  Circuit details, i.e. tracer hardware · CPC title

• G06F11/3404

  for parallel or distributed programming · CPC title

• G06F9/30112

  comprising data of variable length · CPC title

• G06F7/49915

  Mantissa overflow or underflow in handling floating-point numbers · CPC title

• G06F7/507

  using selection between two conditionally calculated carry or sum values · CPC title