Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice

US10884185B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10884185-B2
Application numberUS-201916380111-A
CountryUS
Kind codeB2
Filing dateApr 10, 2019
Priority dateApr 12, 2018
Publication dateJan 5, 2021
Grant dateJan 5, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.

First claim

Opening claim text (preview).

That which is claimed is: 1. A semiconductor device comprising: a substrate having a plurality of waveguides thereon; a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and an active device layer on the superlattice comprising at least one active semiconductor device. 2. The semiconductor device of claim 1 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate. 3. The semiconductor device of claim 1 further comprising a plurality of optical modulator regions within the superlattice. 4. The semiconductor device of claim 3 further comprising vias extending through the active device layer to the optical modulator regions. 5. The semiconductor device of claim 3 wherein the optical modulator regions comprise a dopant. 6. The semiconductor device of claim 1 wherein the at least one active optical device comprises at least one metal oxide semiconductor field effect transistor (MOSFET). 7. The semiconductor device of claim 1 wherein the base semiconductor monolayers comprise silicon. 8. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen. 9. A semiconductor device comprising: a semiconductor-on-insulator (SOI) substrate having a plurality of waveguides thereon; a superlattice overlying the SOI substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; a plurality of optical modulator regions within the superlattice; and an active device layer on the superlattice comprising at least one active semiconductor device. 10. The semiconductor device of claim 9 further comprising vias extending through the active device layer to the optical modulator regions. 11. The semiconductor device of claim 9 wherein the optical modulator regions comprise a dopant. 12. The semiconductor device of claim 9 wherein the at least one active optical device comprises at least one metal oxide semiconductor field effect transistor (MOSFET). 13. The semiconductor device of claim 9 wherein the base semiconductor monolayers comprise silicon. 14. The semiconductor device of claim 9 wherein the at least one non-semiconductor monolayer comprises oxygen. 15. A semiconductor device comprising: a substrate having a plurality of waveguides thereon; a superlattice overlying the substrate and waveguides, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and an active device layer on the superlattice comprising at least one active semiconductor device. 16. The semiconductor device of claim 15 wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate. 17. The semiconductor device of claim 15 further comprising a plurality of optical modulator regions within the superlattice. 18. The semiconductor device of claim 17 further comprising vias extending through the active device layer to the optical modulator regions. 19. The semiconductor device of claim 17 wherein the optical modulator regions comprise a dopant. 20. The semiconductor device of claim 15 wherein the at least one active optical device comprises at least one metal oxide semiconductor field effect transistor (MOSFET).

Assignees

Inventors

Classifications

  • Alternating layers, e.g. superlattice · CPC title

  • Vias, e.g. via plugs · CPC title

  • Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

  • having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation · CPC title

  • having quantum effect structures or superlattices, e.g. tunnel junctions · CPC title

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Frequently asked questions

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What does patent US10884185B2 cover?
A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent…
Who is the assignee on this patent?
Atomera Inc
What technology area does this patent fall under?
Primary CPC classification G02B6/12. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 05 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).