Method for making a FINFET having reduced contact resistance

Patent metadata

Field	Value
Publication number	US-10840337-B2
Application number	US-201816192911-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Nov 16, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

First claim

That which is claimed is:

1. A method for making a fin field-effect transistor (FINFET) comprising:
forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween, at least one of the source and drain regions being divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region, the dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a gate on the channel region;
depositing at least one metal layer on the upper region; and
applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

2. The method of claim 1 wherein each of the source and drain regions are divided into lower and upper regions by a respective dopant blocking superlattice.

3. The method of claim 1 wherein the upper region is raised above an upper surface of the semiconductor fin.

4. The method of claim 1 wherein the lower region comprises a different material than the upper region.

5. The method of claim 4 wherein the lower region comprises silicon; and wherein the upper region comprises silicon germanium.

6. The method of claim 4 wherein the lower region comprises silicon germanium; and wherein the upper region comprises silicon.

7. The method of claim 1 wherein the at least one metal layer comprises a lower metal layer and an upper metal layer different than the lower metal layer.

8. The method of claim 1 wherein the at least one metal layer comprises at least one of titanium, cobalt, nickel and platinum.

9. The method of claim 1 wherein the base semiconductor monolayers comprise silicon.

10. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

11. A method for making a fin field-effect transistor (FINFET) comprising:
forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween, the source region comprising a lower source region and an upper source region divided by a source dopant diffusion blocking superlattice with the upper source region having a same conductivity and higher dopant concentration than the lower source region, and the drain region comprising a lower drain region and an upper drain region divided by a drain dopant diffusion blocking superlattice with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region, each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
the upper drain region and upper source region being raised above an upper surface of the semiconductor fin;
forming a gate on the channel region;
depositing at least one metal layer on the source and drain regions to define respective source and drain contacts; and
applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form respective source and drain contact insulating interfaces between the upper source and drain regions and adjacent portions of the at least one metal layer.

12. The method of claim 11 wherein the lower drain region comprises a different material than the upper drain region; and the lower source region comprises a different material than the upper source region.

13. The method of claim 12 wherein the lower source and drain regions comprise silicon; and wherein the upper source and drain regions comprise silicon germanium.

14. The method of claim 12 wherein the lower source and drain regions comprise silicon germanium; and wherein the upper source and drain regions comprise silicon.

15. The method of claim 11 wherein the at least one metal layer comprises a lower metal layer and an upper metal layer different than the lower metal layer.

16. The method of claim 11 wherein the at least one metal layer comprises at least one of titanium, cobalt, nickel and platinum.

17. A method for making a fin field-effect transistor (FINFET) comprising:
forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween, the source region comprising a lower source region and an upper source region divided by a source dopant diffusion blocking superlattice with the upper source region having a same conductivity and higher dopant concentration than the lower source region, and the drain region comprising a lower drain region and an upper drain region divided by a drain dopant diffusion blocking superlattice with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region, each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
forming a gate on the channel region;
depositing a respective lower metal layer on the source and drain regions to define respective source and drain contacts;
applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the lower metal layers to form respective source and drain contact insulating interfaces between the upper source and drain regions and adjacent portions of the lower metal layers; and
depositing a respective upper metal layer on each of the lower metal layers that is different than the lower metal layers.

18. The method of claim 17 wherein the lower drain region comprises a different material than the upper drain region; and the lower source region comprises a different material than the upper source region.

19. The method of claim 18 wherein the lower source and drain regions comprise silicon; and wherein the upper source and drain regions comprise silicon germanium.

20. The method of claim 18 wherein the lower source and drain regions comprise silicon germanium; and wherein the upper source and drain regions comprise silicon.

21. The method of claim 17 wherein the upper and lower metal layers comprise at least one of titanium, cobalt, nickel and platinum.

Assignees

• Atomera Inc

Inventors

• Takeuchi Hideki
• Connelly Daniel
• Hytha Marek
• Burton Richard
• Mears Robert J

Classifications

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title